[SI-LIST] : Looking inside the IBIS model

Todd Westerhoff (toddw@cadence.com)
Wed, 26 May 1999 14:19:40 -0400

Hi all,

I read the posts on the use of IBIS Cref, Rref, et al, last week with considerable interest. While I saw a lot of discussion around the model parameters themselves (and whether or not they are present in a given model), I didn't see much discussion of how the buffer delay (AKA TIME_TO_VM) fits into the larger scheme of things - namely, the flight times from SI analysis system clock cycle budget.

So, knowing how confusing the subject can be to newcomers (I remember how long it took me to understand it), I took a stab at writing it up. I based this on bits and pieces of presentations I'd already put together, added some new stuff specific to buffer delay, and then added notes. The result is a Powerpoint '97 file, where you can view or print the "notes" pages to see the explanatory text.

The SI-reflector won't post a message longer than 60K bytes, so I can't attach the .zip file (300K). I have uploaded the file to the Cadence ftp server:

ftp://ftp.cadence.com/pub/timing101.zip

for those of your who may care to download it and read it. You comments and suggestions for improvements are appreciated, which I will incorporate as time permits.

As always, YMMV, HTH, HAND (my favorites from last week).

Todd.

<excerpt><bold>

</bold></excerpt> <bold>Todd Westerhoff

</bold><color><param>0000,0000,ffff</param> Technical Marketing
Director | High Speed Systems Design | Performance Engineering

</color><color><param>ffff,0000,0000</param> Cadence Design Systems |
270 Billerica Road | Chelmsford, MA 01824

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email: toddw@cadence.com

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