RE: [SI-LIST] : An Interesting Presentation
Ingraham, Andrew (Andrew.Ingraham@compaq.com)
Wed, 21 Apr 1999 07:09:43 -0500
> On the one hand, I agree with Dr. Johnson's hypothesis that (bus delay) /
> (clock period) is _an_ important yardstick, ignoring risetimes and signal
> integrity problems. He is looking at the bus from the logic, not
> electrical, point of view. You have to make both work; not only do the
> 1's and 0's need to fit the timing constraints, but the electrons and
> millivolts need to fit the electrical constraints to be seen as the right
> 1's and 0's. When the logical bus timing constraints are easy, maybe you
> can relax SOME OF the electrical constraints too.
> On the other hand, I don't see why Ethernet is necessarily any more
> difficult than, say, RAMBUS, despite having 40 times the "difficulty"
> metric. Nor why it is 1600 times more difficult than 66MHz PCI! It seems
> to me that the things that determined Ethernet's need for special low
> capacitance receivers and such, were the electrical constraints, NOT
> timing. So I completely disagree with Dr. Johnson's choice of examples.
> These are cases where the electrical considerations far outweigh the
> simple timing needs, and in my mind they make Howard Johnson's
> presentation fall apart.
> Not having gone to DesignCon99, I didn't actually see Dr. Johnson's
> presentation. I do hope there was more to it than just these slides,
> because they seem VERY thin.
> Andy Ingraham
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