Re: [SI-LIST] : simlifying Spice models

D. C. Sessions (dc.sessions@vlsi.com)
Thu, 15 Jul 1999 15:02:57 -0700

Ron Miller wrote:
>
> Hi guys
>
> I need to reduce the complexity of a very complex spice model to use in
> another larger circuit.
>
> The present model has arrays of 16 cmos transistors in about a dozen places
> on the schematic.
>
> If the models were electrical based I could scale the parameters to reduce the
> arrays to one part. However, the models I have are dimensional.
>
> So, the two approaches I see are :
>
> 1. Simulate the model all by itself to generate a response, and then
> Optimize an assumed electrical circuit to give the same response. or
>
> 2. Use a SPICE to IBIS conversion, and then convert back to SPICE
> with an IBIS to SPICE conversion.
>
> Since I have never used IBIS, and have not kept up to date with SPICE over
> the last 20 years, I do not have a feel for how much time this will take.

Are these arrays in parallel? If so, you can just set M=16 and get on with
your sims. Fond as I am of IBIS, I really don't see it as a time-saver if
you have the transistor-level SPICE deck and a simple reactive environment.

-- 
D. C. Sessions
dc.sessions@vlsi.com

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