Re: Q:Via Capacitance....Re: [SI-LIST] : Pass-through vias as BGA lands (?)

Chandrakant Hemraj Sakharwade (sakh@cadence.com)
Tue, 9 Mar 1999 14:32:57 +0531 (IST)

Daniel,

The value of ~0.53 pF as given in "High-Speed Digital Design"
is for a 16 mil via with 28 mil annular ring and 50 mil clearance
hole in ground plane (for a 63 mil PCB thickness.)

One can reestimate the capaciatance for other geometries
(C = 1.41*er*T*D1/(D2-D1)).

Microstrip with following geometry has 2.6 pF /inch
(Width = 8 mil, height above ground plane = 6 mil,
thickness = 2.37 mil, er = 4.5)

Hope this helps.

-Sakh

Cadence Design Systems

> From owner-si-list@silab.Eng.Sun.COM Tue Mar 9 13:49 IST 1999
> Date: Tue, 09 Mar 1999 08:57:53 +0100
> From: Daniel Roganti <droganti@lucent.com>
> Organization: nsi0414141
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> Subject: Q:Via Capacitance....Re: [SI-LIST] : Pass-through vias as BGA lands (?)
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> All,
>
> Would somebody have some info on what the average Via capacitance would
> be ?
> I recall using a average of 0.5pf per Via.
>
> But now I'm dealing with a 16 Layer PCB and the Vias are 26mils.
> Also, I would expect Blind Vias would have less capacitance than a
> Thru-Hole Via.
>
> I also recall about the Traces having an average Capacitance of
> 1.5pf/inch.
> Would there be any current statistics on this ?
>
> My margin on the Bus Loading is at a minimum.
> We're using the MPC8260(Motorola) and the timing is gautanteed at only
> 50pf if we're expected to run at 66Mhz with 0 Waitstates.
>
> thanks,
> Daniel

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