RE: [SI-LIST] : HSTL voltage levels

Hansel Collins (hacc@tricn.com)
Tue, 03 Aug 1999 15:50:48 -0700

Fab:

I have designed HSTL nets that operate with 1 to 2 loads with clock
speeds
of 150MHz. This is currently shipping in SGI products and has no
problems.
Other systems that I have designed (not in production yet) will operate
up
to 400MHz. The answer is NO to setting Vref to 1.5V. Vref MUST TRACK
VDDQ
and the peak-to-peak noise on Vref must not exceed 2% Vref(DC). The
input
high and low thresholds are Vih= Vref+0.2V (AC) and Vil= Vref-0.2V (AC)
for
single-ended nets. For differential Vdif= 400mV (min) to Vddq+0.6V
(max).
Note: the maximum voltage allowed for VDDQ (your Vtt) is 1.6V so that
the
maximum allowed AC swing is 2.2V. Hence, the 2.5V peak voltage that you
are
seeing is out of spec.

As for Vol and Voh, they would normally swing GND to VDDQ or 1.5V. The
JEDEC
specification specify a maximum output low of Vol= 0.4V (DC) and minimum
Voh
= Vddq-0.4V. This yields worse case noise margins of 180mV (Vil to Vol
DC)
and 80mV(Vil to Vol AC). For the high state a noise margin of 220mV (Vih
to
Voh DC) and 120mV (Vih to Voh AC).

hansel

Hansel A. Collins, CEO
TriCN Associates LLC

Circuit Design, Signal Integrity, and Technology Development

1600 Villa Street Suit 334
Mountain View, CA 94101
Phone : 650 964 7983
Fax : 650 988 6927
Mobile : 650 867 4306
HTTP://www.TriCN.com/

|-----Original Message-----
|From: owner-si-list@silab.eng.sun.com
|[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of fabrizio zanella
|Sent: Friday, July 30, 1999 6:14 AM
|To: si-list@silab.eng.sun.com
|Subject: [SI-LIST] : HSTL voltage levels
|
|
|Hello,
|can someone share experiences with using HSTL as an I/O buffer for
driving
|point to point at 100MHz and faster? What confuses me are the
|Vref and Vtt
|values specified in the HSTL Jedec spec and in data sheets from
|manufacturers - Vref=0.9v, Vtt=1.5v. I have performed some
measurements
|and simulations with the specified Vref level of 0.9V and it does not
make
|sense, the signal swings I see are from 0.7 to 2.5V, therefore there is
no
|margin at the low side. Is it possible to change Vref to 1.5V, like
with
|SSTL and GTLP technologies?
|
|thanks very much,
|
|Fabrizio Zanella
|EMC, Hardware Engineering
|fzanella@emc.com
|508-435-2075, x4645
|
|
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