RE: [SI-LIST] : Different oz copper for grounds

Mckinley, Jory (Jory.Mckinley@compaq.com)
Thu, 23 Sep 1999 21:05:06 -0700

Hello Chris,
One issue that comes to mind while isolating and grounding the thermal
layer
are the signal paths that exist on signal layer one (S1). These
typically
are non-critical and may be static signals. But if they are not in your
case then isolating the thermal plane creates a potentially large return
loop for S1 through the GND layer (not to mention the power loop
return).
My guess is by looking at the complete layup is that S1 is probably for
pads, vias, and quasi-static signals but I figured I would toss it out
there
just in case.

Enjoy,
Jory

Jory McKinley
SI/Timing Consultant
ph: (508) 624-7103
email: jory.mckinley@digital.com

-----Original Message-----
From: Chris Bobek [mailto:cbobek@cadence.com]
Sent: Tuesday, September 21, 1999 12:59 PM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Different oz copper for grounds

Hi all,

Thanks for your responses. First, I need to address the Cadence issue.
Yes, I work for Cadence, but just because I work for a tool vendor
doesn't
mean I know how to use all of their tools (I wish!). I try to learn as
much
as I
can about our tools, but that takes time and we are very busy trying to
design boards. Besides, tools are just half the answer. I would much
rather learn some theory from experts like all of you than how to use a
particular tool
to throw some numbers at me that I don't know how to interpret. You'll
notice people like Howard Johnson don't spend a lot of time talking
about
tools because he wants people to understand *why* things happen, not how
to
punch
buttons and get some results. My goal is to understand *both* sides of
things, the theory, and the tool to help me solve my problem.

Whew, sorry for the bantering, but I just had to say it!

Here's a more detailed description of my problem:

We are building a conduction cooled VME card. Our customer is providing
ALL
of the thermal data and constraints to us (ie., they did the thermal
analysis). They recommended an electrically isolated thermal plane as
layer
2.
This plane will conduct heat from underneath hot components through
thermal
vias that will reside under each hot part. The plane will be exposed at
the
two card edges where it will bond to two wedgelocks. The wedgelocks
will
then couple heat to the cold plate (and to the card cage) that holds the
card. For whatever reason (customer says so), there can be no
electrical
connection between the card cage and the VME card.

Because they did the thermal analysis, there is no question about the
"best"
way to sink heat out of the parts on our board. They already figured
that
out for our application. I don't think they are going to go the 2oz
copper
route, so the last concern seems to be the SI/EMC problem with a
floating
plane. I would appreciate it if someone could ellaborate on that for
me.
Do you think we could make the thermal plane a ground plane, but have
some
kind
of electrical insulator underneath the wedgelocks? I know that will
reduce
the effectiveness from a thermal perspective, but it might be worth it,
no?
Btw, here's what our preliminary lamspec looks like:

S1
Thermal
Gnd
S2
3V
S3
S4
Gnd
S5
5V
Gnd
S6

Thank you very much,

Chris

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