RE: [SI-LIST] : Waveform comparison metrics

tomda (tom_dagostino@mentorg.com)
Fri, 30 Jul 1999 09:17:13 -0700

Let me add one more to Scott's list.

i) The series resistance of the test system used to measure the I/V
information was greater than 5 Ohms.

Good work Scott

Tom Dagostino

-----Original Message-----
From: Scott McMorrow [SMTP:scott@vasthorizons.com]
Sent: Thursday, July 29, 1999 7:24 PM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Waveform comparison metrics

<< File: scott.vcf >> Alex

Correlating waveforms between simulators is relatively easy for Spice to
IBIS
comparisons, since it is absolutely possible to have the time scales line
up exactly. If the launch time of the waveform does not line up, then
there
is already a correlation issue between the simulators and the extraction of
the ibis model.

Now, as far as generating a figure of merit for the correlation, I find
that it
depends on the type of comparison that is being performed. Usually, I
compare the
salient features of the waveform that are important for timing and voltage
accuracy. I compare the difference of threshold crossing times for
multiple
cycles to determine the relative differences over the short and long term
in
complex circuits. I also compare the difference in maximum and minimum
voltage swings throughout the cycle. And then, like most of us, I visually
compare the waveforms by direct overlap. I routinely have simulator to
simulator accuracy of Spice and Ibis simulations that achieve time and
voltage differences of less than 5 ps and 5 mV. If I work hard on the
extraction and IBIS model creation I have seen differences that are
indistinguishable from simulator time step resolutions of 1 ps.

In the case of simulator to simulator comparisions a direct numerical
difference
between the two waveforms is a good figure of merit for accuracy. Yes,
DC offset and timescale offset problems will be seen, but they are real
errors. Maximum time and voltage deltas can be computed.

I routinely have simulator to
simulator accuracy of Spice and Ibis simulations that achieve time and
voltage differences of less than 5 ps and 5 mV. If I work hard on the
extraction and IBIS model creation I have seen differences that are
indistinguishable from simulator time step resolutions of 1 ps.

In the case of simulator correlation to actual measurement ... we all have
some work to do here to come up with some appropriate methods. There are
many variables not under control in real measurements that have drastic
effects on wave shape. Scope input bandwidth, probe bandwidth,
probe insertion loss and loading effects, trace impedance, material
constants,
trace geometry, active device characteristics, temperature, power supply
voltage, power plane noise ... etc ............ arrg! In general, I tend
to
first characterize the board traces as well as possible to adjust the
simulator's field solver to give the same results. Once I know the
characteristics
of the transmission line environment, I then take physical measurements of
the driver launching a wave into the line. TDR physical measurements can
be made of device packages in circuit to determine accurate models for
device packges. With these in hand, I can then measure driver waveforms
at the package pin and record the waveform profile of the launched
voltage ramp. From this, I "tweek" the IBIS model to mimic the
exact waveshape with the V/T table and "adjust" the I/V curve to
give the equivalent driver "ledge" into the the same loading conditions.
In effect, my V/T table and I/V curves are calibrated to the exact loading
condition of the circuit under test. Alternatively, one can pay for
someone
to extract the V/T table and I/V curve for a particular device at a
particular
temperature into a particular loading condition to produce an accurate
IBIS model for the driving device. By the time this is done, the
correlation
is generally left to accurately modeling the input characteristics of the
recieving devices. Alternatively, remove all other recievers from the net
and simulate with only the driver, the board trace, and unterminated
stubs. (Unterminated stubs are the easiest to model :)

If stuff doesn't correlate by this point, then there are some fundamental
assumption which are wrong. The most common is that the driving
device has some sort of feedback mechanism, either designed into
the device, or as part of a parasitic path, or both.

In all the work I have done correlating simulators with each other and
with real devices, I find the following to be true.

1) Correlation result differences between simulators are usually small and
are due to either simplifying assumptions in building the simulation
circuit, or to just plain ole bugs.

2) Major differences between simulators usually are due to basic
bugs and/or very stupid simplifying assumptions.

3) Differences between simulator "models" and real devices are
usually due to poor model extraction methods, unmodeled sections
of I/O circuits, such as ESD clamping structures, misunderstood
fundamental behavior that cannot be accounted for by the modeling
approach, and (my favorite) the manufacturer's model is a just totally
incorrect ... because (and this is a multiple choice):
a) a newbie in the applications department was given the
job
b) the I/O cell spice model was taken from a previous
design
c) special "features" that give the device a perceived
technical advantage are removed from the model
d) special "features" that would reveal device flaws
are removed from the model
e) the package model is "just a guess" (who has time
to do a 3D full package extraction)
f) the package model has been "doctored" to account
for nasty effects (coupling, SSO, return path
problems)
in an extremely approximate way.
g) the model had to be "approved" by the marketing
department to be useful and "valid" for all future
steppings and enhancements of the device
for ever and ever more ... world without end ...
amen.
h) you guys told us to deliver models for the device
and we've never done this before.

Have a good evening,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

"Levin, Alexander" wrote:

> In the course of a design, there are many occasions requiring the comparison > of waveforms to determine "sameness". Several tasks requiring waveform > comparison come to mind: building and checking IBIS models, > comparing/benchmarking simulator tools, and comparing simulated waveforms to > lab measurements. Aside from the basic metrics of rising/falling delay, > ringback amplitude, overshoot/undershoot, is there a repeatable > (automatable?) method which can quantify the degree of matchup between two > waveforms? > > Several approaches come to mind, but each carries its own downfalls. > Waveform subraction: Will provide an estimate of the differences between > waveforms, but is extremely sensitive to any time offset. > Correlation coefficient: Analagous to a dot product of the voltage-time > sample points in each waveform. Doesn't capture absolute DC voltage level > shifts; r^2 offers no information about type of mismatch. > FFT: Can capture similarity in edge rates, ringing period, etc. but key > waveform differences may be masked or lost in high frequency noise seen in > FFT's of digital waveforms. > Overlaying and eyeballing: The human eye is an excellent image processing > device, but the statements "looks good" or "that's a lot of overshoot" are > often too subjective. > Apply basic metrics: Measuring rise/fall delay, ringback, over/undershoot, > ringing period, etc. are typically used. Again, however, the interpretation > of the matchup is subjective. > > I'm not necessarily looking for a catchall solution, but would be > interesting in hearing about any novel approaches people are using. > Waveform overlay will still have its place, but it would be nice to combine > this with less subjective methods. > > Thanks much, > Alex Levin > > **** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****