I would like to know you opinion on this issue. I am interfacing a
state of the art FPGA with a high speed synchronous SRAM device. Since
the interface is bidirectional (the FPGA will read and write data to
the memory) I was wondering what is is the best way to terminate this
bus. My intuition is that if the data lines are not very long, then a
series termination near the FPGA end could have an effect similar to a
series termination near the memory end when the memory is driving the
bus.
I've in the the standard SI book, and haven't found any hint on the
problem.
thanks in advance
-Arrigo Benedetti
-- Dr. Arrigo Benedetti e-mail: [email protected] Caltech, MS 136-93 phone: (626) 395-3695 Pasadena, CA 91125 fax: (626) 795-8649**** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****