[SI-LIST] : Re:

Chang_Ie_Hwaa (ihchang@faraday.com.tw)
Wed, 10 Mar 1999 10:11:28 +0800

John,
The input high Vih and input low Vil for a CMOS chip is the DC SPEC.
If you drive Vil/Vih for "long" anough time, you will finally get
correct
logic. In your case, the most safty way is to measure Vih on the rising
edge of clock signal to Vil on the falling edge of signal. If your
signal slew is still very slow after it fall below Vil, you may need
excess setup time to account for the weak driving capability of input
stage of the signal pin.( Input level determine the gate to source
voltage of CMOS input stage )
Regards,
I.-H. Chang 3/10 '99

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****