RE: [SI-LIST] : BGA vs Leaded - summary

tomda (tom_dagostino@mentorg.com)
Tue, 9 Mar 1999 09:02:02 -0800

Believe it or not there are techniques that can take advantage of bond
wire parasitics to improve the bandwidth of the die to package
interconnect. Tektronix used techniques like T-coils to match impedances
between the die and the package in the early 70's. Just measuring distance
between die and PCB is not adequate, you need to analyze the situation and
apply good analog and RF design techniques to design a package. Obviously
controlled impedance runs to the die pads is the optimal solution but there
are other answers.

Tom

-----Original Message-----
From: john lipsius [SMTP:jlipsius@cyras.com]
Sent: Monday, March 08, 1999 2:46 PM
To: si-list@silab.Eng.Sun.COM
Subject: Re: [SI-LIST] : BGA vs Leaded - summary

<< File: jlipsius.vcf >> Greg,

The regular BGA **does** have bond wires and this can be a problem when
terminating hi-edgerate i/o, around 1GHz in my experience.

The problem is that termination on the pcb can present itself as a resonant
structure
or a significant stub and must be fly-by. Also, the Ball locations should
be closest to
the die to minimize bond wire length in the pkg. and a 4 layer (with pwr,
gnd) BGA
pkg should be used to control the impedance and crosstalk of the critical
io to/from the ball.

Lastly, an excessive ball count pkg is typically required in order to (for
an asic) obtain
enough designer choice to achieve the optimum ball placements cited above.

Flip Chip really improves this situation. The die pad are attached
directly to the pkg.
with attachments right on the die. But new asic physical design tools are
required.

-John

greg kimball wrote:

> All who have contributed.......thanks,
>
> Just wanted to summarize what i have read:
> 1. That the BGA does have inherent lower parasitic L and C (no bond
> wires and no packaging leads) and therefore better interconnect
> transmission properties, - some details were given in the paper
> suggested by Ravider at IBM "Noise computation in single chip...." IEEE.
> (Thanks Ravinder)
>
> 2. Those advantages can easily be squandered by -
> - long leads to the closest decoupling site
> - long leads to the interconnect junctures
>
> 3. Moral of the story ??????
> In order to take advantage of BGA, which does carry a
manufacturing
> cost premium, very careful interconnect strategies my be thought out
> and put in place.
> We have not talked about thermal aspects, but this is another
tricky
> area of consideration - underfills, number of balls to xfer heat out,
> thermal gnd planes, etc, etc
>
> Any parting comments ????
>
> Regards,
> Greg
>
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--
Thanks,
John Lipsius
Member Technical Staff
Cyras Systems, Inc.
46832 Lakeview Blvd.
Fremont, CA 94538
510-623-6631

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