Re: [SI-LIST] : Decoupling caps and power plane effects

ajmani@us.ibm.com
Mon, 17 May 1999 15:05:34 -0600

I am trying to run a similar simulation but in a different way, using IBM's
internal PEEC based simulator. Here, I am modeling every ASIC on the board as a
potential noise source. Bypass capacitors are placed around the ASIC, as would
be done in the actual board, and are modeled with series inductance and
resistance. The simulator injects broadband noise voltage at every source
location (all noise sources are in-phase), and simulations are done in frequency
domain. The simulator results show the noise currents in power/ground planes at
different frequencies, which provide the indication of the effectiveness of
capacitor at that location in suppressing the noise.

Regards, Ravinder
Email: ajmani@us.ibm.com
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