Sync SRAM's should have more than one bypass cap. I recommend an 0603
package by each power pin if you possibly can. If you can afford two vias
per pad, do it. The SRF of 10nF caps before interconnect inductance is
about 50MHz. The AVX parts will only take this up to about 70MHz
best-case. You can push the SRF up by dropping the capacitance, but you
will have to go down to 250pF caps to cover 300MHz( third harmonic ),
assuming zero interconnect inductance. The really nasty part of this is
that your clocks and signals will demonstrate rise times with significant
energy up to and perhaps beyond 500MHz, ( 1nS Tr ).
To bypass cover the high end, your best bet is to use the power and ground
planes as plate capacitors. To get the capacitance up, you need to place
these close together. You can use the Zycon process to get about 2 mils,
although 3 mils in FR4 is manufactured pretty regularly.
The 10uF bulk capacitors have an SRF way down around 1 MHz. This makes
them most useful for power-entry. Your best bet to do this with a pencil
is to do an impedance lot of your bypass scheme against frequency, and
compare that to your current load versus frequency.
At 09:40 AM 7/19/1999 -0400, you wrote:
>What is the best solution for bypassing 100MHz SDRAMs and Syncburst
>SRAM? Is it useful to place a bypass cap at VDD/VDDQ pin along with a
>10uF bulk capacitor near every chip or is this defeating the purpose?
>I am currently investigating the low inductance line of bypass caps with
>reverse aspect ratio from AVX.
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