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From: Doug Brooks [mailto:email@example.com]
Sent: Wednesday, March 17, 1999 5:54 PM
To: Raymond.Anderson@eng.sun.com; firstname.lastname@example.org
Subject: Re: [SI-LIST] : A Question About Power Noise.
Perhaps you can hear my chuckling in the background, here.
Once apon a time, I advocated running traces from caps to devices. My
reason, primarily, was to keep noise off the planes. I took quite a bit of
heat from many people who said that routing to the plane was a MUCH lower
inductance way to route.
Now you provide information that (might) suggest that even if the plane had
NO inductance, there is inductance in the vias getting back and forth from
the planes to the caps and devices. So the planes, in the total picture
might not be the lowest inductance way to route afterall. And,
interestingly enough, Michael Zhang then says the HP (Printer Division)
routes using traces to keep noise off the plane (If I understood his e-mail
Then the argument shifts from inductance to loop area (a view that, at
least I, hadn't heard before). This, in fact, might be a pretty good
argument. Even if the loops on the planes are of similar length, there is
at least some shielding there that does not exist around surface traces.
So here is my challenge to some of you. My company has tried to design,
test, and report on two areas in the past --- the effects of vias on PCB's,
and the effects of 90 degree corners on PCB's. The results of both
investigations appeared in PCB Design and copies are available on our web
site. My company does not have the resources to conduct an experiment on
bypass caps (although we will certainly participate to the extent we can
help). Some of you DO have the resources. So lets have a few people
associated with this group figure out how to design and control an
experiment that will resolve these issues once and for all, and share those
results with the rest of the community.
I hope someone picks up the challenge.
Doug Brooks, President email@example.com
UltraCAD Design, Inc. http://www.ultracad.com
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