[SI-LIST] : Decoupling strategy in tight spaces

Chris Bobek (cbobek@cadence.com)
Tue, 14 Sep 1999 18:18:34 -0700


I am trying to come up with a decoupling strategy for a board I'm
working on. Unfortunately, there are some constraints that make it more
difficult than other boards I've done.

For various reasons (i.e., mil project), we have the following
capacitors to work with:

4700pF -- 0805 (largest value for smallest case size, for our
0.1uF -- 1812 ("")
15uF -- 0.6ohm ESR, 1412

For parts with a lot of switching and I/O, my thoughts were to:
- use a 4700pF at each power pin because it has a smaller case size than
the 0.1uF which will yield lower inductance, thus better response for
higher freq's.
- use a 0.1uF at each power pin for most of the other freq's.
- use the low ESR 15uF where possible to provide large switching

For other, smaller parts, I would just use a mix of 4700's and 0.1's.

Are there any major problems with my reasoning? Does anybody have
"better" recommendations... and can back them up ;-)

I will follow this question up with another later, concerning capacitor
placement and vias.

Thank you,


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