# Re: [SI-LIST] : high-power board

Larry Smith ([email protected])
Mon, 5 Apr 1999 09:28:40 -0700 (PDT)

Pat - I believe that you are into a very important area, one that is
becoming an important issue for all of us. 1000 Watts is not too far
out of line for multiple processor systems these days. I am a little
surprised that you are still at 5 Volts. Many modern systems are
wanting to see that kind of power at less than 2 volts.

Some simple calculations will give you a good indication of where you
are on your power planes. Given 1000 Watts and 5 Volts, you are
consuming 200 amps. If you want to keep your power supply regulation
within 5% x 5V = 250 mV, you will have to meet a target impedance of
1.25 mOhm. The first thing to look at is your power plane resistance.

One-half ounce copper planes are .7 mils thick and have about .97 mOhms
per square. Assuming a power and ground plane, your DC distribution
resistance is about 2 mOHms per square. One square is more than you
can tolerate, even at DC. The problem becomes more interesting at high
watts. If it is large enough, it will just heat up, not burn. The
biggest challenge will be to regulate the voltage at the several loads
with DC drop being a big issue.

The direction that we are headed is multiple pairs of 1 oz planes in
parallel. The best bet is to keep the DC resistance under 20% of the
target impedance. That way you have a good chance of staying within
the power supply tolerance spec and won't dissipate too much power in
the board.

regards,
Larry Smith
Sun Microsystems

> From: "Pat Zabinski" <[email protected]>
> Date: Mon, 5 Apr 1999 09:28:48 -0500
> To: [email protected]
> Subject: [SI-LIST] : high-power board
> Mime-Version: 1.0
>
>
> We're looking into a board that has much higher power requirements
> than we're familiar with, and I'm looking for some advice. Here's
> a summary of the board:
>
> * roughly 1000 Watts (1 KW) off a single +5 V DC supply
> * full-swing CMOS
> * ~50 ASICs
> * 200 MHz clock and data paths
> * up to 300 simultaneous switching outputs per chip
> * between 12x12 and 24x24 inch multi-layer PCB
> * ASIC packages have yet to be determined/designed
>
> To some extent, we have a good handle on the standard SI issues, but
> we're looking for input in two areas: decoupling and power.
>
> With 300 full-swing switching outputs per chip, what's the best
> (or a good) way to decouple the supply? First, at the chip-level.
> Second, at the board-level.
>
> At this high of power level, what are the primary concerns? How
> do we best address them? Is there a limit on how much current
> a half-ounce copper sheet in FR4 can tolerate? How much current
> can I push through a standard via before it melts? How can
> we effectively remove the heat?
>
> Any suggestions, ideas, and paper references will be appreciated.
>
> Thanks,
> Pat Zabinski
>
> --
> Pat Zabinski ph: 507-284-5936
> Mayo Foundation fx: 507-284-9171
> 200 First Street SW [email protected]
> Rochester, MN 55905 www.mayo.edu/sppdg/sppdg_home_page.html
>
>
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