Re: [SI-LIST] : Estimating DIMM Power Consumption

Russell Rapport ([email protected])
Fri, 27 Aug 1999 10:19:45 -0700

Messages sorted by: [ date ][ thread ][ subject ][ author ]
Next message: Dave Hoover: "[SI-LIST] : FR-4 and PCB Tolerances"
Previous message: Allen Wang: "[SI-LIST] : PCB impedance variation v.s. layout pattern"
Maybe in reply to: Chris Heard: "[SI-LIST] : Estimating DIMM Power Consumption"

A good rule of thumb is to multiply individual 128Mbit TSOP component
ICC2,
3, and 6 values by 18 (for idle and power down modes). For active modes
(ICC1,4, or 5), add one 128Mbit TSOP ICC3N value to the ICC1, 4, or 5
values,
then multiply by 18. The registers and PLL currents will add another
100-250mA. You can also contact marketing at my company, Staktek, and
ask for
our SDRAM product specs.

Chris Heard wrote:

> All,
>
> I'm trying to find if there are any ways to estimate 512Mb DIMM power
> consumption other than adding up all of the operating currents in burst
> mode. If I do this the numbers get very high and I am guessing that true
> operating DC power consumption will be less.
>
> Anyone have experience in this area?
>
> Chris
>
> *******************************
> Chris Heard
> Principal Hardware Engineer
> Rajmataj, Inc.
> 100 Locke Dr
> Marlboro, M.A. 01752
> Work: 508-486-9660 x325
> Mobile: 508-277-5780
> email: [email protected]

**** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****

Next message: Dave Hoover: "[SI-LIST] : FR-4 and PCB Tolerances"
Previous message: Allen Wang: "[SI-LIST] : PCB impedance variation v.s. layout pattern"
Maybe in reply to: Chris Heard: "[SI-LIST] : Estimating DIMM Power Consumption"