[SI-LIST] : Simulating Meander Delay Lines

Roy Leventhal (Roy_Leventhal@mw.3com.com)
Wed, 22 Sep 1999 13:28:14 -0500

All:

Has anyone successfully (as defined by lab measurements matching simulator
results) simulated a bus net with a delay (meander/serpentine) line in it? If so
whose software tool did you use?

The net I'm simulating is about 35 inches in length with a 17.5 inch meander
line in it. Etch width is narrow enough on some portions (4 mils) and via count
high enough (18+) that parasitic resistance could also be a factor. My tool
extracted the net using a "2-1/2D" field solver. I would expect corner and self
coupling on the line as routed to be a factor.

Other information: 1 driver and 9 receivers, clock at 83 MHz and driver edge
rate at about 13v/nS.

Reply to me directly if you wish:
rleventh@mw.3com.com

Regards,

Roy Leventhal

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