RE: [SI-LIST] : response to semiconductor I/O edge rates

Muranyi, Arpad (arpad.muranyi@intel.com)
Thu, 15 Jul 1999 16:25:51 -0700

Roy,

I really don't want to get into a huge discussion here, because I am too
busy
and I don't think this is such a big deal. I probably shouldn't have said
anything in the first place. I am just writing again, because you asked me
specific questions, and I feel I have to answer them.

I am NOT saying that I want one part that fits all. I guess, I was just
trying to
say that as an IC vendor I would not like to have to make custom parts for
every
customer who happen to be running their designs at different clock rates.

I also understand that most modern designs have fairly well defined
interfaces at
specific clock rates. However, since not all ICs are made to operate on a
bus
with a well defined (single) clock rate, the IC vendor may not know what
clock rate
the IC should be designed for, so programmable edge rate (or custom design)
may be
necessary. This, however, increases the price of the parts, which people
may not
want to pay for.

Also, I only brought up the all too familiar(?) 74 series because it was
mentioned
before in the thread with some very interesting reports on how they are or
are not
comparable even if they are claimed to be identical.

And to answer Tom's most recent question, "if you have a 4 MHz circuit why
are
you using 100+MHz parts"? This may be happening in a lot of cases because
the
old parts may not be available any more, and because old fabs with large
feature
sizes may not be around any more. Or, old parts don't have some features
that
newer parts have. And, as someone said it in the thread, the edge rates are
a
direct consequence of smaller and smaller sizes. To reduce the speed of
bleeding
edge technology you have to design slew rate controlled buffers. The next
question
then is what that controlled slew rate should be, and we are back at the
beginning
of the circle.

Arpad
============================================================================
====

-----Original Message-----
From: Roy Leventhal [mailto:Roy_Leventhal@mw.3com.com]
Sent: Thursday, July 15, 1999 1:34 PM
To: si-list@silab.eng.sun.com
Subject: RE: [SI-LIST] : response to semiconductor I/O edge rates

Arpad,

You can always find an exception to a rule. That's one reason why there
will
always be work for SI engineers. Glue logic jelly bean parts, available in
many
different technologies at many different speeds are not a big problem here
at
3Com. Nor, do I see our circuit designers mis-applying them.

Big, proprietary, in development ASICs that you get locked into before you
are
even aware of the surprises are the problem.

For a supplier to say "well too bad, caveat emptor" is suicidal for both
supplier and customer. Jelly bean parts that are supposed to be all things
to
all people are dismal failures for controlling quality. They're all over the
place from lot to lot. They do nothing well beyond saving their maker a pile
of
money. Assuming anybody wants them.

The Japanese implemented something called "mass customization" on a stable,
standard process base. Lots are targeted at specific slots in a process
window.
Besides, I've been hearing of various output circuit strategies to
supplement
and complement the process control levers.

Are you telling me that you want life to be simple? Make one part for all
applications, let the process fall where it may, don't even worry about
binning
out the result and let the customer worry about it?

Maybe I misread your ideas.

Roy

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