I think your and Howard's point of view are both correct. We SI people see
risetime as a more relevant parameter than clock period. But the digital
designers that we work with can understand the bus delay and clock period
more clearly since the risetime is of only secondary concern to them (if it
is a concern at all). The value of Howard's "bus timing ratio" is
communicating a general level of difficulty of SI to digital designers in
their own terms. It is "a key indicator", but not the only key indicator.
Charles Hill, consultant
At 09:53 AM 4/17/99 -0700, Abe Riazi wrote:
> Recently, I reviewed an interesting paper by Dr. Howard Johnson, which
>had been presented at DesignCon99. It is a PDF file (busarch.pdf)
>entitled: "Bus Architecture & Timing", available at the High Speed
>Design Web Site: http://www.signcon.com/
> The paper evaluates design difficulty of several different buses in
>terms of bus timing ratio defined by [( bus delay ) / (clock period)].
>The results are summarized below:
> Bus: PC-AT, Bus timing ratio: 0.008,
>Mode: Slow , Design: Easy;
> Bus: PCI, Bus timing ratio: 0.062,
> Mode: Skew, Design: -------;
> Bus: RAMbus, Bus timing ratio: 2.5,
>Mode: Distributed clock, Design: -------;
> Bus: Ethernet 10BASE-5, Bus timing ratio: 100, Mode:
>Time-space, Design: More difficult;
> In the final slide it is stated: " The ratio (bus delay)/(clock
>period) is a key indicator of bus design difficulty".
> Admittedly, I was surprised by the conclusion and method of analysis
>employed by this article. Here, a parameter dependent on the PERIOD is
>used to evaluate difficulty of bus design. It seems to me that
>"Critical Length" is preferable for appraisal of design (or simulation)
>complexity of a high speed bus architecture. The Critical Length Lc
>varies with the RISE TIME (i.e. Lc = k * Tr / D , where Tr is the Rise
>Time ), rather than with the period or frequency.
> Your comments are appreciated.
> Best Regards,
> Abe Riazi
> Anigma, Inc.
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