1) correlating buffers (only) into the standard load (usually, a pure
resistive load)
2) correlating buffers with an "odd-load" (we used 6" of tline to 10pf to
GND) to verify complex reflections
3) correlating a two pin buffer net (buffer to buffer) to validate buffer
loading characteristics
We then repeat steps (1) thru (3) for the packaged device model, that
includes the parasitic effects between the die pad and device pin.
Using this process of correlating buffers and simple loads first, followed
by complex loads and packages, we have been able to make tremendous
improvements in our ability to translate and correlate simulation models
from different formats.
The goal is perhaps a little bit different than the original one -
verifying model accuracy - but the process and end results are the same.
Todd.
At 11:14 AM 7/21/99 -0500, [email protected] wrote:
>Mark,
>
>In addition to the standard load used to specify Tco (clock-to-out time)
and the
>two 50 Ohm loads mentioned by DC Sessions, I would like to recommend two
other
>loads. These loads can be used to correlate models with hardware and
behavioral
>(IBIS) with structural (SPICE) simulations.
>
>The first load is an open transmission line probed at the far end. This load
>allows you to verify the complex reflection coefficient of the driver,
which is
>a combination of the output impedance and the various capacitances associated
>with the output. You need to make the transmission line long enough
relative to
>the edge rate so that the wave has a chance to bounce around 2 or 3 times.
>
>The second load is a transmission line and a receiver or tri-stated driver.
>This load double-checks the previous load and adds the turn-on
characteristics
>(both ac and dc) of any clamps that may be present.
>
>It's also very important to verify input and output IV curves and pin
>capacitances. I have found that a TDR is a pretty handy capacitance meter.
>
>Some of my colleagues and I wrote up a document that provides a wealth of
>details on how to do model correlation. It's called "The IBIS Accuracy
>Specification," and you can find it under "accuracy" on the IBIS web site:
>www.eigroup.org/ibis/ibis.htm. There's even a test board design there that
>demonstrates how to make some of these measurements in the lab.
>
>Good luck in your work. Many of us users are encouraged to find vendors like
>you who are doing their best to insure model integrity.
>
>Greg Edlund
>Advisory Engineer, Critical Net Analysis
>IBM
>3650 Hwy. 52 N, Dept. HDC
>Rochester, MN 55901
>[email protected]
>
>
>---------------------- Forwarded by Gregory R Edlund/Rochester/IBM on
07/21/99
>10:59 AM ---------------------------
>
>
>Mark Nass <[email protected]> on 07/20/99 07:33:05 AM
>
>Please respond to [email protected]
>
>To: [email protected]
>cc:
>Subject: [SI-LIST] : Best type of models, edge rates & load
>
>
>
>
>
> There has been some discussion recently about parameters of parts
>specified into 40pf caps and accuracy of models. I generate this type
>of data for our devices for our own use and our customers. So I am
>curious as to what people think would be the optimal way to generate
>Tco, Tsu, jitter parameters and IBIS models so that they would be confident
>they were getting exactly what they needed for signal integrity and timing
>analysis. Any feedback?
>
>Mark Nass
>
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>
>
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>
>
Todd Westerhoff
Technical Marketing Director | High Speed Systems Design | Performance
Engineering
Cadence Design Systems | 270 Billerica Road | Chelmsford, MA 01824
ph: (978) 262-6327
fx: (978) 446-6798
email: [email protected]
internal information website: http://www-ma.cadence.com/~toddw
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