[SI-LIST] : high-power board

Pat Zabinski (zabinski.patrick@mayo.edu)
Mon, 5 Apr 1999 09:28:48 -0500

We're looking into a board that has much higher power requirements
than we're familiar with, and I'm looking for some advice. Here's
a summary of the board:

* roughly 1000 Watts (1 KW) off a single +5 V DC supply
* full-swing CMOS
* ~50 ASICs
* 200 MHz clock and data paths
* up to 300 simultaneous switching outputs per chip
* between 12x12 and 24x24 inch multi-layer PCB
* ASIC packages have yet to be determined/designed

To some extent, we have a good handle on the standard SI issues, but
we're looking for input in two areas: decoupling and power.

With 300 full-swing switching outputs per chip, what's the best
(or a good) way to decouple the supply? First, at the chip-level.
Second, at the board-level.

At this high of power level, what are the primary concerns? How
do we best address them? Is there a limit on how much current
a half-ounce copper sheet in FR4 can tolerate? How much current
can I push through a standard via before it melts? How can
we effectively remove the heat?

Any suggestions, ideas, and paper references will be appreciated.

Thanks,
Pat Zabinski

-- 
  Pat Zabinski                                     ph: 507-284-5936
  Mayo Foundation                                  fx: 507-284-9171
  200 First Street SW                     zabinski.patrick@mayo.edu
  Rochester, MN 55905       www.mayo.edu/sppdg/sppdg_home_page.html

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