[SI-LIST] : Handy little models

D. C. Sessions (dc.sessions@vlsi.com)
Thu, 15 Apr 1999 16:01:50 -0700

I've been meaning to publish this little thing for a while.
Basically, it's a simple behavioral model which does a decent
job of imitating a very good CMOS output stage. Its output
impedance remains constant during transitions (I wish!), its
switching is perfectly linear, and it has zero intrinsic
delay (!).

On the other hand, it *is* sensitive to its supplies. The
outputs are operated off of vccr and veer, which can be
connected to inductive, resistive, or otherwise nonideal
sources. The supplies couple into the outputs as the
Thevenin voltages but also by modulating the output
impedance via a simple gate-starvation approximation.

Being behavioral it's VERY fast to simulate, and being more
or less perfect within its limits it's useful as a stopping
point for I/O design.

.PARAM
+ core = 3.3 $ Nominal core supply voltage
+ ring = 3.3 $ Nominal I/O supply voltage
+ Vt = 0.5 $ Output device threshold voltage
+ GN( g ) = 'MAX(g-Vt,0)/(core-Vt)'
+ GP( g ) = 'MAX(g-Vt,0)/(ring-Vt)'

.SUBCKT driver i z vccr veer vddc vssc
+ z0=50 $ Nominal output impedance
+ rleak=1E6 $ Channel leakage resistance
+ imax=600m $ Output saturation current
+ cpad=2.0p $ Output capacitance

R1 vccr z rleak
G1 vccr z
+ CUR='v( vccr, z )*GP( v( vccr, i ) )/Z0'
+ MIN='-imax' MAX='imax'

C11 vccr zpr 'cpad/2'
R11 zpr z 20
R12 z znr 20
C12 znr veer 'cpad/2'

R2 z veer rleak
G2 z veer
+ CUR='v( z, veer )*GN( v( i, veer ) )/Z0'
+ MIN='-imax' MAX='imax'

.ENDS driver

-- 
D. C. Sessions
dc.sessions@vlsi.com

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