[SI-LIST] : Chip level Vs Board level SI

Arun Chandrashekar (carun@cedt.iisc.ernet.in)
Thu, 15 Apr 1999 23:41:29 +0530

Hello all,
I need some information on factors that distinguish signal
integrity problems at the chip level and at the board level. I
personally feel that board level SI problems are more prominent as I do
not have much idea about the chip level SI problems. Also, most articles
I come across do not seem to address the SI problems at the chip level.
Can u help me throw light on this point and clarify ?
Thanks and Regards
ARUN C
Research Associate
CEDT, Indian Institute of Science
Bangalore, Karnataka, INDIA
560012
Ph: +91-80-3341810
FAX: +91-80-3341808
Homepage URL: http://shravana.cedt.iisc.ernet.in/~carun

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