Re: [SI-LIST] : coming up with average power estimates for buffers

D. C. Sessions (dc.sessions@vlsi.com)
Tue, 03 Aug 1999 15:46:21 -0700

Adrian Shiner wrote:
>
> D.C, You have made the classic mistake of oversimplification of the load presented to the supply. In your scheme of things, the system would dissipate very little power within the computing hardware. Current flows in circuits
> which are not in seies with the capacitances which you use in your equations. Statistical averaging...that is part of the power of RSS in the real engineering world where practical fast solutions matter.

You might be surprised how accurate this model actually is. As you note,
fast practical solutions are the objective and extraneous detail just gets
in the way. In particular, the question had to do with the amount of power
dissipated and not its spacial or temporal distribution.

First: as for the dissipation being very small: I simply calculated the total
supply current. As long as that current is provided at a low real impedance,
the dissipation will be almost all in the load, and the time distribution of
the power (over one UI) is of no importance. The dissipation will of course
be *located* in the driver and the terminators; in the nominal case where the
drive impedance matches the line impedance the current will be (Vcc/2Z0) for
a duration of 2Tp at some repetition rate. Curiously, Q=(Vcc/2Z0)(2Tp)
comes out to Vcc*Cline (surprise!)

In the case where the driver has Rs >> Z0 the currents will be smaller and
last for a longer time, but the total charge transfer will be the same, as
will the total work per transition (W=Q*Vcc/2); of course both rising and
falling edges dissipate heat but the total work input to the system is going
to be Q*Vcc regardless. Conservation laws are your friend.

In the Rs<<Z0 case the terminators can play a part. In that case the total
charge initially transferred to the line is greater, but some of it is
returned to the supply either through the driver or the load (eg clamps).
Again, the location of the power dissipation varies both in time and space
but the net result is the same: W=Q*Vcc=Vcc*Tp/Z0

Again, all of these assume that the line actually reaches equilibrium
before the next transition. *Usually* a safe assumption, but getting
iffier every year.

The one I/O dissipation path that isn't part of this analysis is the driver
crowbar current. Now while it's *possible* to misdesign a driver to pass
large amounts of crowbar current, there's no excuse for it. All of the
drivers I've designed pass crowbar charges a small fraction of their own
capacitive transition charges, and that wasn't even a primary design
constraint, just a check that we run. I really see no reason why others
should be any different.

> "D. C. Sessions" wrote:
>
> > Doug Yanagawa wrote:
> > > Pat Zabinski wrote:
> >
> > > > One other point to note: as we increase the transmission line
> > > > length, the RMS power goes up as well (as expected). However,
> > > > this trend continues to a certain point, then the power actually
> > > > reduces with increased line length. Can someone explain why
> > > > the RMS power would be reduced with increased length? We're only
> > > > seeing a small percentage change (~10-20%), but it's got
> > > > me curious.
> > >
> > > When the transmission line gets long relative to the switching
> > > frequency, the driver is not completely charging and discharging the
> > > net. Hmmm, maybe we could solve the worlds energy problems. But the
> > > theoretical power mins might have nasty harmonics associated with them.
> >
> > All of the RMS-vs-peak etc. stuff has been fun, but mostly irrelevant.
> > Assuming a reasonably stiff power supply (safe bet) and no shunt termination
> > (iffy) each rising transition will induce a delta-V equal to the supply
> > voltage on some amount of capacitance (the falling transitions return the
> > charge to ground.) The line capacitance is very nearly the trace capacitance
> > plus load devices up to prop delays half of the line high time; for most
> > systems this is a safe assumption. If the system actually has ballistic
> > signals -- the UI is less than the round-trip delay -- then running
> > without shunt terminations is REALLY bold.
> >
> > SO! In the absense of highly structured activity, there will be a rising
> > edge approximately once in four UIs, each of which will charge the line to
> > Vdd. Power is thus (Vdd)(Vdd)(Cline+Cload)/UI -- good old CFV**2
> > Clocks, of course, are the quintessential example of "highly structured
> > activity."
> >
> > If the line *is* shunt terminated, the power consumption becomes largely
> > independent of frequency and is the statistically weighted sum of the
> > power in the high state and the low state.
> >
> > --
> > D. C. Sessions
> > dc.sessions@vlsi.com
> >
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-- 
D. C. Sessions
dc.sessions@vlsi.com

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