Re: [SI-LIST] : Seeking SI models for memory DIMMs.

gheiler@kodak.com
Thu, 5 Aug 1999 17:06:43 -0400

From: Gregory N Heiler

Hello:

Another approach, that I used to model a DIMM model, is to write an EBD
based on the Intel PC100 DIMM Specifications. The specification specifies
impedance, vias, topology and trace length ranges. Along with the Memory
Chip IBIS Models, an EBD can be written from this information. It won't
match a specific vendors module exactly but I believe it would be fairly
representative for any vendor who's module complies with the PC 100
Specification. At least I'am hoping it will be fairly representative. To
qualify the design, one may want to run several simulations with different
vendor's memory chip ibis models, which can easily be swapped in and out .
I found this approach fairly quick to execute and seems to have given good
results. It also seemed like a reasonable approach given the multisourcing
of components issue.

Regards;

Greg Heiler

Todd Westerhoff <toddw@cadence.com> on 08/05/99 11:17:26 AM

Please respond to si-list@silab.eng.sun.com

To: si-list@silab.eng.sun.com
cc: (bcc: Gregory N Heiler/249007/ELEPROD/EKC)
Subject: Re: [SI-LIST] : Seeking SI models for memory DIMMs.

Kim and Scott,

It's true - you can go to developer.intel.com, search for "SDRAM" to find
reference designs (.brd files) for DIMMs and, for that matter, RAMBUS RIMMs
and continuity modules. Some of these files (the SDRAM DIMMs, for example)
are in Allegro V8 format, and you may find that the database versions have
to be "upreved" to work with current versions of software. Since these are
Allegro .brd files, you'll need to have access to the Allegro "extract"
utility to get data extracted for your use.

You should also note that the stackup settings in the reference designs are
not correct (SDRAMs in particular). The correct stackup information is
shown on one of the drawing layers (as a diagram), but is not, in fact,
setup correctly in the "cross section" part of the database. If your
translator tries to read the stackup information in the database, you will
get the wrong data, and consequently, the wrong field solutions.

It's an easy matter to edit the stackup (requires Allegro), or to edit the
extracted data to correct it, but you need to be aware of the issue.

Todd.

At 09:46 PM 8/4/99 -0700, you wrote:
>kim
>
>contact micron,hyundai, samsung, viking, ... and request that they
>provide you ibis ebd models of their dimm modules.
>
>In addition, you can down the .brd files for pc-100 dimms
>from the intel web site. Just search for pc100 and you should
>find them. You can then translate them into your particular
>simulator format, apply standard sdram ibis models and
>be off and simulating.
>
>regards,
>
>scottt
>
>Kim Helliwell wrote:
>
>> Anyone else doing PC motherboard design? How do you get or
>> fudge models for the memory modules on the board?
>>
>> The obvious thing is to request the .brd file for the DIMM
>> from the manufacturer, but for some reason, they are
>> reluctant to part with this information. I can't imagine
>> why :-) Actually, I really can't; there can't be that much
>> proprietary content in such a small board, after all.
>>
>> Neophyte that I am to the SI world, I'm blocked, but I just
>> bet there is some dodge around this problem that someone
>> else has come up with. If so, would you be willing to share?
>> Am I overlooking something obvious?
>>
>> --
>> Kim Helliwell
>> Senior CAE Engineer
>> Acuson Corporation
>> Phone: 650 694 5030 FAX: 650 943 7260
>>
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Todd Westerhoff
Technical Marketing Director | High Speed Systems Design | Performance
Engineering
Cadence Design Systems | 270 Billerica Road | Chelmsford, MA 01824

ph: (978) 262-6327
fx: (978) 446-6798
email: toddw@cadence.com
internal information website: http://www-ma.cadence.com/~toddw

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