Re: [SI-LIST] : How to simulate the jitter of the part?

Stephen Peters (sjpeters@ichips.intel.com)
Thu, 24 Jun 1999 08:38:49 -0700

Harold Snyder wrote (in part);

> Shubin,
<snip>

> Once you have converted to ECL or PECL
> your noise should not get worse than it was at the input to the 100ELT22
> unless you have noise on your power lines.

From my understanding, most PLL jitter comes from power and ground noise.
Instead of connecting a perfect voltage source to the VCC lead, should
probably carefully model the power delivery and ground return paths to/from
the part and inject a little random noise into the voltage source.

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