RE: [SI-LIST] : Anyone doing SI simulations for Pentium II

PETER_ARNOLD@hp-santaclara-om3.om.hp.com
Fri, 10 Sep 1999 10:09:44 -0700


I am working with Intel's slot 2 models (i.e. Pentium II Xeon CPUs) in
Quad format, which appear to be built the same as the slot 1 models
under discussion. I'd like to share my experiences.

Intel provides a driver/receiver model connected to a package model
connected to a cartridge trace model connected to a connector
approximation. The cartridge traces are modeled as transmission lines,
the connector as lumped elements (these models can be downloaded from
Intel's public website.)

I obtained the spice model of a slot-2 connector and had it converted
to a quad "topspec" model, which I now use in place of Intel's lumped
version. The results are actually not much different in our
simulations, but at least take into account that different pins have
different lengths.

I would prefer to have some subset of the actual cartridge layout
database so that coupling information could be extracted, and lengths
are accurate for each net.

As the mail below points out, there is not enough information for
return path effects to be modeled. In fact, as my ground-referenced
trace leaves the motherboard and enters the cartridge, it may find
itself adjacent to a different voltage plane altogether. The models
don't allow me to know this. The return current may be forced into a
large deviation to find a way from my ground plane to this other
voltagge plane, probably through the nearest decoupler. This is the
reason that all slot-2 designs have 15-20 ceramics with low-inductance
plane connections (e.g. double vias) spread alongside the slot-2
connector.

I tried to get stackup and coupling information so I could attempt to
model large measured SSO pushout effects in the first generation
slot-2 parts. Intel documents recommend that we should not model this
but allow an extra 800ps (a lot!) in my timing equations as a safety
margin. I'd like to claim some of that 800ps back through more
complete modeling and simulation.

Intel does not like to release information about the cartridge layout
and stackup. I believe they are concerned that it would be difficult
to keep such information up-to-date as the layout gets altered, but
mainly they don't like to let proprietary information like that out
the door even to trusted OEMs. Well, fair enough, but as we get closer
to Merced this level of modeling will not cut it any more. To their
credit I think Intel has recently launched an effort to rationalize
its various internal modeling and simulation practices.

peter arnold

______________________________ Reply Separator _________________________________
Subject: RE: [SI-LIST] : Anyone doing SI simulations for Pentium II
Author: Non-HP-apanella (apanella@enteract.com) at HP-Boise,mimegw18
Date: 9/9/99 8:25 PM

Hi All...

This Intel model is real interesting...

A couple of cautions...
* I do not see any signal to signal coupling in this model. Signal to
signal coupling (up to 5th order effects) is valuable for crosstalk
concerns.
* The inductance given is for a "Loop Inductance". As such, return path
inductance is not identified in the model. The return path inductance is
required to determin ground bounce.

There is also another reason that I can think of to create a module mated to
a connector...
The module is inserted into the connector... as such... whatever planes are
in the PCB also get inserted into the connector... along with all kinds of
FR4 dielectric material. All this material, when mated, will intersect with
EM field lines generated by the signals traveling through the combination of
the connector pins and the module. Bottom Line, I guess what I am saying
(or agreeing with) is that:

unmated connector model + unmated edgcard pcb
DOES NOT EQUAL
mated interconnect response

Taking it a step further.... maybe not in slot 1.. but in the not so
distant future generation of edgecard interconnects.... the connector
terminal geometries will have MAJOR impact on transmission line performance.
As such a "general connector model" will not be the best solution. Instead,
a mated connector model, from where the current leaves the base board to
where current exits the plastic (or maybe where current exits the gold
fingers) would be a much better solution. Yes, the gold finger design does
need to be included in the connector model.

But for right now... assuming the edgerates are slow enough... and
depending on the simulation precision required... the approach listed below
may work acceptably.

Personally, I would use caution when using the model below for anything less
that 1 nS..... and would put a VERY high priority on other finding other
modeling options for simulations with risetimes faster than 500 pS....

Now... a little more to the problem...
Is it possible to REDUCE (not remove) the package parasitics listed in the
model such that the connector effect is not used???.... then... get a .pkg
model for the connector MATED to a PCB that has a stackup similar to the one
in the PII board.

(We are talking IBIS models right??)

This will work better..
because in a pkg model it is possible to create somewhat of a coupled
matrix. Then install this package file into your simulator.....

Cautionary Note:... it is my understanding that some simulators do not know
what to do with a package model with coupling. I have no idea what
SpectraQuest or Cadence support... nor do I know which simulators support
couple pkg IBIS format models.



Gus Panella
Molex Incorporated
apanella@enteract.com




> -----Original Message-----
> From: owner-si-list@silab.eng.sun.com
> [mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Todd Westerhoff
> Sent: Thursday, September 09, 1999 7:22 PM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Anyone doing SI simulations for Pentium II
> boards?
>
>
> Hi all,
>
> Sorry for the delay in reply.
>
> Actually, the Intel processor cartridge models have typically included the
> parasitics for the connector as part of the catridge model. The reasoning
> is simple; there's no point in modeling/simulating the cartridge
> by itself,
> since it never gets used that way.
> The cartidge parasitics are also normally not lumped, but include a
> collection of transmission line statements in addition to lumped
> parasitics
> for things like pad and pin capacitance ... careful inspection of the .EBD
> file will tell you which is which:

> <SNIP>

> At 12:41 PM 9/8/1999 -0700, you wrote:
> >I face the following puzzle in running a signal integrity
> >simulation on Pentium II board. I'm using SpecctraQuest
> >and Signoise, in case this matters.
> >
> >I have a Pentium II IBIS model (which I converted to Cadence's
> >.dml format). This model appears to model all the parasitics
> >of the Slot 1 board in a lumped manner; I presume that the
> >model includes parasitics up to the edge fingers. (Does anyone
> >know different?)
> >
> >I also have a model of a Slot 1 connector in SPICE format. Quite
> >aside from issues of how this model is to be used (I'm trying to
> >get the answer to that from the supplier) is the issue of how to
> >include the Slot 1 connector parasitics in the simulation. At
> >first, I thought I could use a design link and treat the connector
> >as a cable connecting the main board and the Slot 1 module, but I
> >think that requires that I have the "board layout" of the Pentium
> >module. The next thought was to treat the connector as a package, but
> >this doesn't work since the Pentium II module is already a package
> >model. So I'm left with adding the connector parasitics in some
> >fashion to the existing Pentium II model. I just want to check
> >that this is in fact the correct approach, or else find out whether
> >I'm giving up too soon on one of the first two approaches mentioned,
> >or whether there's another approach I haven't considered.
> >
> >I'm sure I'm not the only one facing this, so how are others
> >solving it?
> >
> >
> >--
> >Kim Helliwell
> >Senior CAE Engineer
> >Acuson Corporation
> >Phone: 650 694 5030 FAX: 650 943 7260
> >
> >**** To unsubscribe from si-list: send e-mail to
> majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
> si-list, for more help, put HELP. si-list archives are accessible at
> http://www.qsl.net/wb6tpu/si-list ****
> >
> >
> >
>
> Todd Westerhoff
> Technical Marketing Director | High Speed Systems Design | Performance
> Engineering
> Cadence Design Systems | 270 Billerica Road | Chelmsford, MA 01824
>
> ph: (978) 262-6327
> fx: (978) 446-6798
> email: toddw@cadence.com
> internal information website: http://www-ma.cadence.com/~toddw
>
><SNIP>


**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In
the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list
archives are accessible at http://www.qsl.net/wb6tpu/si-list ****

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****