Re: [SI-LIST] : 20-H Rule for Power Planes

Chris Padilla (cpad@cisco.com)
Wed, 26 May 1999 14:26:35 -0700

A valid question, indeed. I just make sure that when I do such a
thing, I have no traces referencing the power plane in the area of
interest where I want to put some ground plane. In the PCB
designs and on the types of boards that are designed at Cisco, I
have such a luxury as to be able to put power and ground planes
on the same layer if necessary...not always, but sometimes. It is
the actual design of the board that provides this option. I don't
know how valid it is in general...it is probably the exception rather
than the rule.

Like has been said throughout this thread, it all depends on your
design. Maybe 90% of the people laying out boards cannot do what I
am able to...if they wanted to that is.

Hope that helps

----->Chris

>Hi Chris,
>
>I have a couple of questions about how you are doing your board design
>with reference to the description you gave. If I understand correctly,
>you have voltage and ground planes on the same layer. I'm assuming that
>you have signal traces that traverse the inter-plane moats. If this is
>the case, how do you provide for your return path, given that the trace
>will reference tow different planes?
>
>
> Regards,
>
> Ron
>
>
>On May 26, 12:00pm, Chris Padilla wrote:
>> Subject: RE: [SI-LIST] : 20-H Rule for Power Planes
>> Consider a multi-layer board of 16 layers (4 GND, 2 PWR, 8 internal
>> routing, 2 external routing). My goal with this board is to make it
>> a Faraday cage as much as possible.
>>
>> In one direction, I've almost got this due to the ground and power
>> planes. But it's the sides or edges of the board where I could see
>> a lot of leakage. (Yes, the populated top and bottom layers radiate
>> and are "holes" in the cage. Some of these vendor's chips make my
>> job a challenge as well.)
>>
>> I then do a ground stitch around the perimeter of the board along with
>> a metal trace on all layers as space permits. This automatically
>> forces a cut-back of the power plane of anywhere from 50 - 100 mils.
>> And why is a non-uniform stitching better than a uniform stitich? The
>> point is to close up the edges of the board as much as possible and
>> get a Faraday cage effect.
>>
>> Also, why flood a (typically noisy) power plane into areas that might
>> not need the particular voltage? I only do this if I have a lot of
>> traces referencing the power plane and ripping it out would cause
>> image currents to take big loops. Otherwise, I see if I can fill in
>> the rest of the power plane with a ground plane.
>>
>> I don't have a shred of data to suggest that this design works better
>> than equally sized ground and power planes but, it makes sense to me
>> to try and go for the Faraday cage effect--at least a Faraday cage
>> for your inner layer traces.
>>
>> Thanks,
>>
>> Chris Padilla
>> EMC Engineer
>> Cisco Systems
>>
>> >I agree with Larry on this and would add that at the frequencies of
>> >interest
>> >a server board with a setback of one plane vs another MAY constitute a
>> >reasonably good slot antenna. In fact, at some conditions, the edge of
>> >the
>> >board becomes a slot radiator such that stitching becomes necessary.
>> >Lest
>> >you become lazy, stitching left to the layout designer and not defined
>> >by
>> >the SI engineer has been known to increase the slot radiation.
>> >Uniformity
>> >of stitching is not good. My point on all of this is to analyze on a
>> >use
>> >and technology basis and don't over generalize to a blindly followed
>> >rule.
>> >
>> >Tomm
>> >
>> >-----Original Message-----
>> >From: Larry Smith [mailto:ldsmith@lisboa.eng.sun.com]
>> >Sent: Tuesday, May 25, 1999 2:45 PM
>> >To: si-list@silab.eng.sun.com
>> >Subject: Re: [SI-LIST] : 20-H Rule for Power Planes
>> >
>> >
>> >I don't believe in the "20-H Rule". Suppose the power plane was at
>> >3.3V and the ground plane was at 0V. It would be easy to reconfigure
>> >the system so that the "power" plane is at 0 volts and the"ground"
>> >plane is at -3.3V. Does this mean that the power plane should now be
>> >bigger than the ground plane?
>> >
>> >The only difference between the power and ground plane is that one is a
>> >0V and the other 3.3V WRT (...thats with respect to, lest I start
>> >another discussion...) earth ground. But even this is not true in a
>> >battery operated system. In any modern digital system, the impedance
>> >between the power and ground plane is much less than 1 ohm well into
>> >the EMI frequencies.
>> >
>> >The ground plane probably has a path out to frame ground and eventually
>> >earth ground somewhere. But if that path is more than an inch long, it
>> >is going to be well over 10 nH. Ten nH is 1 Ohm at 15 MHz (Z=jwL) and
>> >higher impedance at higher frequencies. So, above 15 MHz, the voltage
>> >between the power and ground planes is insignificant compared to the
>> >voltage across the earth ground connection.
>> >
>> >The power and ground planes should be exactly the same size. To make
>> >one larger than the other will simply have the effect of turning nice
>> >diffential currents into common mode current and common mode
>> >radiation.
>> >
>> >regards,
>> >Larry Smith
>> >Sun Microsystems
>>
>>
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>>
>>-- End of excerpt from Chris Padilla
>
>
>
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