Re: [SI-LIST] : Clock Skew Measurements

David Chengson (chengson@juniper.net)
Fri, 8 Oct 1999 18:48:49 -0700 (PDT)

Alex-
This is not an answer to your question, but a
related question...

Does Phillips offer an LVDS clock buffer? If so,
can you point me to a datasheet? I might be interested
in designing in this part.

Thanks
Dave
> Date: Fri, 08 Oct 1999 17:28:13 -0600
> From: alext <Alex.Theodorou@abq.sc.philips.com>
> MIME-Version: 1.0
> To: si-list@silab.eng.sun.com
> Subject: [SI-LIST] : Clock Skew Measurements
> Content-Transfer-Encoding: 7bit
>
> 10-8-99
>
> Hi SI Gurus,
>
> Anybody out there have any ideas on how to do production
> testing of clock output skew (output pin to output pin)
> on a clock distribution chip?
>
> I've got 2 different chips.
>
> The first chip has 1 PECL input and 10 PECL outputs.
> The maximum input frequency is 1.5 GHz, and the
> maximum clock output skew is spec'd at 35ps.
>
> The second chip is a lot like the first except that it's
> got an LVDS input and LVDS outputs. The specs on this one
> are 800 MHZ max input frequency and the maximum clock output
> skew is spec'd at 35ps.
>
> I'm somewhat constrained by the capabilities of my tester
> (Credence Vista Logic). Maybe I need to use some indirect
> technique with active circuitry on the load-board?.
>
> Thanks in advance for your suggestions.
>
> Regards,
>
> Alex Theodorou
>
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>

Dave Chengson Juniper Networks www.juniper.net
chengson@juniper.net W: (650) 526-7989 FAX 650 526-8001

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