I have really appreciated the ongoing discussion about edge rates that my
original beef has kicked up and the many related topics it has opened up.
Lest we loose sight of my original beef it is this:
A consequence of shrinking feature size to get more on a die and faster
processing speeds is this: Edge rates have been kicked into warp speed: This has
lead most boards potentially having a signal integrity problem on every net on
the board --> where the edge rate bears no relation - way too fast - to the
intended application it creates "make work" unneccesary problems that cuts into
his/her chances of competitive success.
So long as SI engineers don't understand this and don't push back on their
suppliers to see if the problem can be fixed at the SOURCE, they don't
understand that they're hired to make a contribution, not engage in busy work.
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