Hi SI Gurus,
Anybody out there have any ideas on how to do production
testing of clock output skew (output pin to output pin)
on a clock distribution chip?
I've got 2 different chips.
The first chip has 1 PECL input and 10 PECL outputs.
The maximum input frequency is 1.5 GHz, and the
maximum clock output skew is spec'd at 35ps.
The second chip is a lot like the first except that it's
got an LVDS input and LVDS outputs. The specs on this one
are 800 MHZ max input frequency and the maximum clock output
skew is spec'd at 35ps.
I'm somewhat constrained by the capabilities of my tester
(Credence Vista Logic). Maybe I need to use some indirect
technique with active circuitry on the load-board?.
Thanks in advance for your suggestions.
Regards,
Alex Theodorou
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