Re: [SI-LIST] : Traces Over Plane Clearances

Jeff Seeger ([email protected])
Mon, 09 Aug 1999 04:50:28 -0400

At 09:22 AM 8/6/99 -0700, Dave Hoover wrote:
> >I have a customer who has a 2000+ I/O BGA with
> >tight pitch. They are using 2 track routing to
> >escape the device on the PCB. At the device,
> >the traces cross over the edge of the reference
> >plane clearances.
> snip <
> >My question is that the customer is afraid the short
> >distances without the reference plane will impact
> >his electrical performance properties.
> >The problem I face is currently the clearance size
> >is reduced to the point that it can't be manufactured.

Hi Dave!

While you are getting many correct philosophical responses
I think your problem is of smaller scope than the community
is responding to.

If I hear you correctly, and this is an issue I see also,
the manufacturing driven clearance on the planes is a bit
larger than combined positive via pad size, trace-to-via
space, and the trace width. This causes the trace to pass
tangentially over the void in the plane associated with an
adjacent via. So one could say that the return path is "a
little stretched", rather than clearly broken.

Where the routing is set up for two traces to pass between
the escape vias, certainly the returns for those two traces
will be co-mingled at this web. This greatly increases the
prospects for crosstalk, which of course is already an issue
on closely spaced conductors in parallel at today's tight

What specific degradation may occur in the signal I can't
say, but if I understand the situation correctly each signal
may have dozens or hundreds of these small displacements
in the return path so any effect will be added many times.

My question to Dave is, "If plane copper weights are kept
the same as the positive layers, why does the manufacturing
community seek on the order of twice as much clearance?" Or
in other words if you can hold the positive pad to tangency
why would plane clearances need to be any bigger than the
positive pad size plus 2X the nominal spacing?

My question to the SI community is, "Isn't this happening to
you constantly already, especially given that registration
of layers on boards is rarely perfect?"

Our attempt as solving this problem has been to try to keep
plane metal under at least a portion of the trace at worst
case tolerances, but this is not always possible without an
argument like the one that sent Dave here....

Regards to all,

      Jeff Seeger                         Applied CAD Knowledge Inc
      Chief Technical Officer                  Tyngsboro, MA  01879
      jseeger "at" appliedcad "dot" com                978 649 9800

**** To unsubscribe from si-list: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at ****