I presume you don't want to model this question with IBIS or SPICE, so I'll give
you a simple pragmatic suggestion.
Beg, borrow, steal or create an output IV characteristic curve that closely
approximates the source (series) terminated driver of interest. Draw a load_line
across the driver IV curve that intersects the characteristic curve at its 50%
(voltage swing) point with one terminus on the Vdd or voltage swing rail value.
The impedance of the load line you just drew is a perfect match for the
conditions of the driver curve. If done at typical, the min/max deviation is
usually tolerable, but rigorous engineering would see you making sure.
As a gross metric, I have used these drivers over a fairly wide range. The
combined effective impedance, including FET and output resistance, worked well
for me into 45-55 ohm t-lines. I don't recall the vendor (IDT?), so you
definately need to check your own. However, get real suspicious if your analysis
yields t-lines much beyond the 40 to 60 ohm range for a 25 ohm series terminated
Brad Henson, Engineering Fellow
Raytheon Systems Co.
Roman Seifert <Seifert@ali.com.au> on 10/09/99 06:05:33 PM
Please respond to email@example.com
cc: (bcc: Bradley S Henson/RWS/Raytheon/US)
Subject: [SI-LIST] : internal series resistors
There are clock buffers with internal dumping resistors in outputs in range
around 25ohm on the market.
Would anybody out there have an idea about recommended track impedance for
buffer ouputs configured as a simple point to point connection?
Sydney - Australia
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