Re: [SI-LIST] : response to semiconductor I/O edge rates

Roy Leventhal (Roy_Leventhal@mw.3com.com)
Fri, 16 Jul 1999 12:19:54 -0500

To All, or No One In Particular:

Which came first: The chicken, the egg, or the ruptured duck?

We're sitting here with a programmable part that I can only deal with in a
horse-and-buggy fashion
(funny how that "buggy" word keeps turning up in talking about EDA) on a
current hot project.

Wouldn't even have found out much about the lack of implementation of
programmable devices in IBIS
if I hadn't been working on another issue: A supplier (different one folks) who
doesn't seem to understand
the [ Pin ] keyword and the necessity to tell the simulator, by pin number,
which I/O cell characteristic to use.

Say, D.C. how long have the conventions for the [ Pin ] keyword been published?

Damm! N'other burr under my saddle!

Roy

"D. C. Sessions" <dc.sessions@vlsi.com> on 07/16/99 11:13:11 AM

Please respond to si-list@silab.eng.sun.com

Sent by: "D. C. Sessions" <dc.sessions@vlsi.com>

To: si-list@silab.eng.sun.com
cc: (Roy Leventhal/MW/US/3Com)
Subject: Re: [SI-LIST] : response to semiconductor I/O edge rates

Roy Leventhal wrote:
>
> Good points about etch length and edge rates.
>
> Somewhere else in the discussions the issue of programmable drive was also
> brought up. We are using progarmmable drive strength and a fixed series source
> terminator (selected by daughter card loading) in at least one instance.
>
> Does anyone know a signal integrity simulator that is up to snuff on IBIS 3.2
> especially with regard to the conventions on programmable devices and has
> automated the handling of such parts?

The EDA members of the IBIS committee report that their managements have
assigned IBIS 3.x support a low priority due to lack of customer demand.

--
D. C. Sessions
dc.sessions@vlsi.com

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