While I cannot comment specifically on what Duet is doing, I have seen
interesting things from a number of vendors that makes me take these
things with an extra grain of salt.
For those with an interest, the Fabless Semiconductor Association (FSA) has
a modeling interest group and www page. Similar issues (ESD, parasitic
extraction, wire & package modeling) arise there from time to time.
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On 30-Mar-99 email@example.com wrote:
> There is a little bit shock to me when I read your message. In
> our company, a new process or a new library must be qualified
> by a real product, abeit both can be made with the same pilot
> run. Although not all the io cells can be put in the
> sample product,, that will be ok because they share the same
> scheme of ESD design. We will have to negotiate to our
> quality manager just if you need to change a metal
> mask and claim that your new design is till said to be qualified.
> (Usually metal connection has less to do with the basic
> Raymond Leung
> Lynne Green <firstname.lastname@example.org> on 30/03/99 11:09:45
> Please respond to email@example.com
> To: firstname.lastname@example.org
> cc: (bcc: Raymond Leung/QSA/AU)
> Subject: Re: [SI-LIST] : Package Parasitics Modelling
> 10K protection??? Many of the 0.25um-and-under processes get 1K to 4K.
> Watch your library suppliers (in-house or custom). Some say "designed to
> but do not tell you what they actually achieve. Sometimes, the first ESD
> results come from customers (i.e. you!), not their own tests. (This is for
> reasons: 1. They don't do test wafers on every process and every I/O cell,
> 2. Designers want to use the libraries today, not wait 3-6 months for ESD
> Also re edge rates: some interface specifications include edge rate
> requirements (such as PCI 3.3V, which is 1-4 V/nsec). Edge rates are often
> limited at the I/O to reduce ringing amplitudes and improve settling time.
> This is an old trick borrowed from telegraph and telephony technology.
> Lynne Green
> Signal integrity engineer (available for hire, thanks to Duet
> resume available on request.
> On 29-Mar-99 Christian S. Rode wrote:
>> Still, 3 ohms (?) is much better than 0.05 ohms. I guess I wrote that
>> last message from an obsolete perspective. In days gone by I think
>> they intentionally used to add a poly serpentine resistor (over thick
>> field oxide) to limit the discharged current. How they get to 10KV
>> input protection today is beyond my ken.
>> A modern model might then be 3 ohms in series with
>> protection diode capacitance + 100 ohms (several squares of
>> 20 ohm /sq diffusion/poly) in series with the input gate capacitance
>> tomda wrote:
>>> "diodes" can easily get to over 100 mA before the voltage across the
>>> is 1 volt.
>>> Tom Dagostino
>>> -----Original Message-----
>>> From: Christian S. Rode [SMTP:email@example.com]
>>> Sent: Monday, March 29, 1999 11:16 AM
>>> To: firstname.lastname@example.org
>>> Subject: Re: [SI-LIST] : Package Parasitics Modelling
>>> A question about IBIS input models. I assume a good portion of the
>>> of these models (C_comp) is associated with the input protection
>>> and that
>>> there can be significant resistance between that capacitance and the
>>> not modeled in (earlier) IBIS models (and the EIA FAQ's "it's included
>>> in the I-V characteristics" isn't relevant). 50 milliohms (or
>>> for R_pkg will
>>> give an unnaturally high-Q for the input model. What would be a range
>>> numbers for
>>> R between the L and C? (I'm currently guessing 100 ohms)
>>> Chris Rode
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