> Any one got some info about what exactly Intel/motherboard
> designers/Rambus have done to screw up the signal integrity when using 3
> RIMM slots in a now-indefinetly-delayed Camino-based PC?
Canceled. No point in being mealy-mouthed about it.
> Here's a link in case you haven't heard about this problem:
My sources (TANS) inform me that it's a matter of clock alignment with
data under extremes of crosstalk, etc. If you start out with a 1400 ps
unit interval (UI) (remember this isn't actually the advertised 800 MT/s
but the already-derated 700) and start subtracting for bit-to-bit skew,
jitter, SSO, etc. they were *supposed* to have 140 ps around the clock
at the receiver for a sample window. In real life it turns out to be
about 40 ps instead.
Apparently the original SI analysis neglected the crosstalk contribution
from the fine-pitch, no-interleaved-grounds connectors for the RIMMs.
The passthrough RIMM obviously makes matters worse both by extending the
signal paths -- through a connector, twice! -- as well as on the MB by
Contrary to the spin control appearing in the press, this is a pure SI
problem and not actually a flaw in the Camino chipset. Unless, of course,
you consider the use of Rambus memory to be a flaw of the chipset. Also
interesting, my sources (TANS) also say that this isn't news to Intel
engineers; they've known about it for months but in the rather tense
political environment at Intel the news didn't make it to the adminisphere.
The phrase "career-limiting move" have been heard a lot lately.
There's an utterly MARVELOUS story here. I've always been a big believer
in the Horrible Example school of engineering education, and watching
the world's largest semiconductor company crater in an extremely public
way over mismanaged signal integrity should be very, very useful in the
years to come.
-- D. C. Sessions email@example.com
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