Re: [SI-LIST] : Pass-through vias as BGA lands (?)
Pat Zabinski (email@example.com)
Tue, 2 Mar 1999 06:39:01 -0600
On Mar 1, 10:29pm, Jeff Seeger wrote:
> Subject: Re: [SI-LIST] : Pass-through vias as BGA lands (?)
> Arrigo Benedetti wrote:
> > snip <
> > In order to keep fabrication costs
> > low the consultant advocates to use pass-through vias as BGA
> > lands. He thinks that this will make his life much easier since every
> > FPGA pin will be accessible from all layers, and the board more easily
> > testable. I don't like this idea since:
> > 1) The AC return currents in the power planes will be forced to follow
> > horrible paths between the vias.
> > 2) During soldering of the BGA package the solder of the balls, once
> > melt, could be sucked into the holes, giving bad contacts. Would
> > filling the vias with extra solder help ?
> > I'm not an expert on PCB construction techniques so I would really
> > appreciate to have some feedback and advice on these issues,
> > especially 2).
> What is the pitch of the BGA device, and is it a full
> array or a peripheral array?
> Let's take the common example of a fully populated .050"
> pitch device first:
> It is customary in working with BGA devices to put a small
> via offset from the actual land, so that soldermask may
> provide isolation for the flowing solder from the barrel
> of the via hole. Your concern with the draining of the
> molten solder is exactly the issue unless you move to a
> different fabrication method for making solid copper vias
> By keeping this via small, a reasonable web of copper can
> be retained on the plane for power distribution and signal
> return path.
> By polarizing the direction in which this "dog bone" is
> routed, i.e. top-left quarter of the device routes toward
> 10:30, top-right routes toward 1:30 etc. a larger etch path
> to the center of the device is created, effectively making
> the "swiss cheese" area one quarter the size of the device.
> For devices of lower pitch this becomes more difficult.
> At a 1mm pitch there may no longer be room for a distinct
> via separate from the ball attach pad. Something more
> like an "8" is used, again being sure to keep a web of
> solder resist (mask) between the edge of the ball attach
> pad and the barrel of the via hole. Again, using properly
> small via holes the clearance on the plane layer can be
> made to allow a web of copper for your return path - if
> there is sufficient room between the vias for a trace
> there should also be room for a return path (albeit not
> very wide). This does intrude on return path but I cannot
> quantify how much impact. I can say that we've worked on
> product exceeding the signaling speeds you mention with
> this technique.
> When the pitch decreases to .8mm and under it is usually
> not possible to keep the via in the pattern without more
> costly fabrication technology. Thankfully most of the
> devices of this category that I have seen are not fully
> populated, giving the possibility of bringing a surface
> wire to an area with more space for vias (as long as that
> space doesn't belong to the next device <g>).
> Such devices also start stressing other activities such
> as bare board test and assembled board test access.
> Board thickness makes a big difference in possible via
> geometries, the objective being to minimize the aspect
> ratio. Also suggest using >= 170oC Tg laminate, to
> minimize the rate of thermal expansion at soldering temps
> (give those small vias a chance).
> I see I've run on a bit. Hope I've helped.
> Jeff Seeger Applied CAD Knowledge Inc
> Chief Technical Officer Tyngsboro, MA 01879
> jseeger "at" appliedcad "dot" com 978 649 9800
> Printed Board Implementation Services http://appliedcad.com
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>-- End of excerpt from Jeff Seeger
"Ditto" to what Jeff says above. Sounds like he's got some good
experience in the area.
One additional piece of information that can sometimes help. In
most CAD tools, there are several options to generate the ground
and power plane artwork. One of the defaults that many tools
use is to place a copper capture pad on each and every layer.
When a signal via passes through a ground plane, the pad will
have a small "void" ring around it to avoid shorting the
signal to the ground. For some applications, this is just
However, to avoid the "Swiss cheese" effect, or at least reduce it,
make sure the ground and power plane artwork is generated in
"negative" film using "anti-pads". With this approach, the
artwork will show where metal is-not (vs positive which shows
where metal is). Then, the signal via locations will have
a smaller void in the plane without the capture pad.
Depending upon the PCB technology you're going with, using anti-pads
can generally shrink the size of the voids by 10-15 mils, thus
providing a better return path.
Pat Zabinski ph: 507-284-5936
Mayo Foundation fx: 507-284-9171
200 First Street SW email@example.com
Rochester, MN 55905 www.mayo.edu/sppdg/sppdg_home_page.html
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