The return path will be broken in the area where the trace is not over a
ground plane. The current will be forced to go in another path in the
ground plane. This path can be modeled as a shorted transmission line
stub. The stub length will be loaded by the dielectric so the electrical
length will be longer than for free space. This modelling method is based
on the duality between slots and dipoles (used a lot in antenna work).
Note the shorted stub is inductive until 1/4 wave resonance, then turns
capacitive. With your dimensions, it sounds like the resonance will be way
into the GHz. Remember also, this stub is a common element for several
circuits so the crosstalk comes into the picture.
Chuck Hill, consultant
At 09:22 AM 8/6/99 -0700, Dave Hoover wrote:
>I have a customer who has a 2000+ I/O BGA with
>tight pitch. They are using 2 track routing to
>escape the device on the PCB. At the device,
>the traces cross over the edge of the reference
>plane clearances. The microprocessor and
>clocks currently run at ~1 GHz (headed above 3 GHz).
>The distance across that clearance would be
>less than .020" in length. There is a copper
>web of around .008" between the plane
>clearances (thinking adequate signal return path).
>My question is that the customer is afraid the short
>distances without the reference plane will impact
>his electrical performance properties.
>The problem I face is currently the clearance size
>is reduced to the point that it can't be manufactured.
>Faced with a dilemma, so I went to the pros.
>**** To unsubscribe from si-list: send e-mail to
firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE
si-list, for more help, put HELP. si-list archives are accessible at
**** To unsubscribe from si-list: send e-mail to email@example.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****