That applies for off-chip loads. For on-chip loads, the current
return loop comprises both, the positive and the ground rail (for
full CMOS output swing), independently of the output switching
direction. Also I guess that most of the on-chip supply noise
results from dI/dt drop. So if the effective inductance from the
external power supply or nearest decoupling capacitor to the power
and ground internal rails is approximately the same, the dI/dt noise
should be symmetrical in both rails.
Jose Luis Gonzalez
-- Now at: Electrical and Computer Engineering Department University of Arizona, Tucson AZ 85721, USA Phone: Office (520) 621 6023 Lab (520) 626 7078 Fax: (520) 621 8076 E-mail: [email protected]Permanent address
____________________________________________________________________________ | OOO Dep. d'Enginyeria Electronica | C/. Gran Capita s/n Modul C4 | | OOO Univ. Politecnica de Catalunya | 08034 Barcelona (Spain) | | OOO | Tel. +34 93 4016748 | | UPC | Fax +34 93 4016756 | | | E-mail: [email protected]|
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