1. You're right that the current path is forced to deviate, increasing the
return "loop" and therefore the inductance/impedance. However, in many, if not
most, of our multilayer boards, the path deviation to the nearest via or de-cap
is small compared to the rise times. This means the deviation can be thought of
or modeled as a small lumped parameter discontinuity. In practice, even a 25ps
rise time TDR head travels about 150 mils during its transition. Most of our
"fast" edges are 10 times that.The first order amount of degradation to be
expected is just a matter of electrical distance of the discontinuity WRT rise
time.
2. Field solvers (2D or other) usually solve a capacitance matrix based on
conductor-plane potentials, then calculate inductance and various impedances
(even/odd modal). Since the fringe field falls off away from the conductor, I
don't think the location of current is ever directly considered unless you
describe the field boundary conditions such that there are discontinuities under
the conductor. You can convince yourself by doing a simple 2D model with an
infinite plane, then reducing it until it approaches the width of the conductor.
I've done it and it convinced me the parasitics and impedances reported are
completly consistent with the high freq. current distribution models. Before we
had good 3D field solvers, I used to run a 2-pass model where I simulated
current going around gridding in ground planes by doing 1 pass with a finite
plane under the trace, then another pass with the signal over a gap and ground
traces (not plane) off to the sides. The reported (averaged) impedances matched
test board measurements pretty well.
It would be interesting to engage someone like Eric Bogatin to help us fully
explore this aspect of field solvers. Is he on this list? Is he still with
Ansoft or is he full time consulting?
just my 2cents...
Brad Henson, Engineering Fellow
Raytheon Systems Co.
bhenson@west.raytheon.com
gedlund@us.ibm.com on 09/30/99 11:12:13 AM
Please respond to si-list@silab.eng.sun.com
To: si-list@silab.eng.sun.com
cc: (bcc: Bradley S Henson/RWS/Raytheon/US)
Subject: [SI-LIST] : the old high-frequency return current
model
Shoot! I was out of town and missed one of the most interesting discussions of
the year! (Plane-jumping return currents) So at the risk of re-opening this
thread, filling all your mailboxes again, and being branded an outcast, here
goes. (Remember, that delete button is only a few inches away...)
You're all familiar with this picture of high-frequency return current bunching
up under the signal trace, right? According to the picture, it dies off pretty
quickly as you move along the x-axis away from the trace. Well, I've been
considering rules for the area density of ground vias and decoupling capacitors,
and it occurs to me that if this picture were true, then the only place for a
ground via or capacitor is within 2-3 trace widths of the signal via in
question. (Which is, for most of our applications, absurd.) Otherwise I'd be
forcing the return current out of that very tight loop, increasing the
inductance, adding a discontinuity, generating plane noise, emissions, and all
those nasty things. Now, I know that boards work quite well up to a few hundred
MHz with considerably less than 100 de-caps per square inch! So where's the
discrepancy? Is there a hole in my fairly simplistic, qualitative analysis? Or
is this just like everything else: knowing how some parameter varies between
the end cases is much harder than analyzing the end cases?
On another tangent, I believe 2-D field solvers make the assumption that the
return current is evenly distributed across the surface of a plane when you ask
them to compute C, L and Z for a given cross-section. Doesn't this also
conflict with the high-frequency current distribution picture?
Eagerly awaiting your answers and hoping I have time to read them,
Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com
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