Re: [SI-LIST] : Edge rates

D. C. Sessions (dc.sessions@vlsi.com)
Fri, 16 Jul 1999 09:02:43 -0700

Roy Leventhal wrote:
>
> Fabrizio,
>
> Interesting.
>
> Also, what I'm seeing is that simple edge rates, as opposed to a full V-T [Rise
> Waveform / Fall Waveform] curve gives you very misleading results on complex,
> multidrop backplane busses. If you want to see the effects of controlled edge
> rate / soft turnon-turnoff parts, such as GTLP, you need those curves. A
> straight dV/dt_r and dV/dt_f hard turnon-turnoff driver contains much more high
> frequency content and will show much more ringing in a simulation.

I'm probably sounding like a broken record in this regard. Sorry.

The problem is that real-world applications are far more impacted by the
di/dt of a driver than with the dv/dt of the wave when it hits the load.
The dv/dt numbers we see published are usually into a 30-50 pf load, so
they are far more representative of the output impedance than of the
"event edge rate" -- the slew rates in the predriver stage. The data
sheet numbers, thanks to that honking great lowpass filter of a load,
have all of the interesting data smeared out.

The trouble is that, as manufacturers, we have this one little obstacle
to doing better characterization: customers. Not necessarily you guys,
but collectively including your PAs and test engineering groups. In
JEDEC JC-16 meetings we've had some long discussions about trying to
provide characterization into more realistic loads, and the conversation
goes something like this:

1) We HAVE to provide TTL-type 45-pf load values because the customers
reject anything 'nonstandard' as 'specsmanship'.
2) The customer components/test engineering groups insist on having no
more than one test condition for each parameter.
3) The design community insists that the IBIS models and the data sheet
use consistent test conditions so that the simulations match up
3) Therefore, we can't provide anything other than the 45-pf load data

Now personally this sounds a lot like rationalization from our collective
marketing groups. That doesn't make it totally bogus, though, and it's
a tangled enough mess that it's going to take collective effort from
several directions to unravel it.

> "fabrizio zanella" <fzanella@fishbowl02.lss.emc.com> on 07/16/99 06:45:33 AM
>
> Please respond to si-list@silab.eng.sun.com
>
> Sent by: "fabrizio zanella" <fzanella@fishbowl02.lss.emc.com>
>
> To: si-list@silab.eng.sun.com
> cc: (Roy Leventhal/MW/US/3Com)
> Subject: RE: [SI-LIST] : Edge rates
>
> Regarding edge rates of devices, here's a point which has not been brought
> up. Edge rates are characterized by semiconductor manufacturers into
> lumped loads, which means nothing if the customer is using the parts to
> drive backplane signals. We've found consistently that published driver
> edge rates are 800ps to 1ns faster when these same drivers are driving a
> backplane with multiple loads (ie 1.5ns data sheet tr/tf is really
> 0.5-0.7ns in system). It has been our task to tell the logic manufacturers
> how fast their device edges really are, therefore causing problems with
> ringing, multiple reflections, etc.
>
> Regards,
> Fabrizio Zanella
> EMC, Hardware Engineering
> fzanella@emc.com
> 508-435-2075, x4645
> -------------
> Original Text
> From: "tomda" <tom_dagostino@mentorg.com>, on 7/15/99 1:54 PM:
> To: smtp@Eng@EMCHOP1["'si-list@silab.eng.sun.com'"
> <si-list@silab.eng.sun.com>]
>
> Besides the edge rate differences between different IC manufacturers, the
> output impedance will differ significantly. Again using your ABT example,
> the output impedance for National, TI and Philips are significantly
> different in both the pull up and pull down characteristics. I have
> measured many devices from all three of these ABT suppliers.
>
> Another point of interest is the clamping characteristics within the same
> family from different logic vendors. Some vendors of LVT have a good Vcc
> clamp while another has a clamp that seems to disappear after 100 mV.
>
> Tom Dagostino
> ICX Modeling Group
>
> -----Original Message-----
> From: jaydiep@us.ibm.com [SMTP:jaydiep@us.ibm.com]
> Sent: Thursday, July 15, 1999 7:25 AM
> To: si-list@silab.eng.sun.com
> Subject: [SI-LIST] : Edge rates
>
> I appreciated Jan Vercammen sharing his edge rate data with the group; it's
> nice
> to have some real data that's without the usual marketing spin. One
> caution
> based on my own measurements is that one should not assume that logic
> families
> sourced from multiple suppliers will have the same characteristics. There
> are
> many different kinds of cross-license agreements that range from mask
> sharing
> (same circuit topology and device geometries, but may be different process)
> to
> only what I would call name-sharing (same DC specs. and prop. delays,
> different
> functions, and VERY different edge rates). To illustrate the latter case
> using
> ABT (an instance of name-sharing), which at least originally was built by
> two
> suppliers (TI and Philips), the rise and fall times for the one supplier's
> parts
> were at best half of those from the other. According to the one supplier,
> their
> engineers had designed edge rate control into their drivers, where the
> other
> supplier either had not, or had used different assumptions. Edge rates or
> rise/fall times were not included in datasheets at that time, but have more
> recently been included in some cases.
>
> One also must worry about what happens when someone gets the idea to cost
> reduce
> the parts by building them in some new, smaller feature size IC process,
> which
> reduces device capacitance and therefore rise/fall times (without edge rate
> control). I've been (as many other IBM designers have) an advocate of edge
> rate
> control for a long time, because at some point everything becomes a
> transmission
> line otherwise. Some circuit designers listen better than others.
>
> Jay Diepenbrock
>
> Senior Engineer
> Interconnect Technology & Qualification
> IBM Global Procurement, B8UA/061, RTP, NC
> Phone: 919-543-8804 Fax: 919-543-3642
> Email: jaydiep@us.ibm.com
>
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-- 
D. C. Sessions
dc.sessions@vlsi.com

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