The simple answer is that this is a big, proprietary development ASIC. The
designer never had any intention that it should have such a fast edge rate. As
a matter of prudent checking he had me check the signal integrity once we got
the IBIS model and partially routed board. That's when we discovered that the
edge rate was so fast. The semiconductor house had never given us a heads-up
that the edge rate was likely to be so fast. Or so I understand it. Now the semi
house is telling us they can't do anything about it.
It is possible that the circuit designer knew about the edge rate earlier than I
think and was hoping that some simulation or layout/routing magic pixy dust
would be sprinkled on his circuit. I don't think I'll ever know the answer to
that. I do see wishful thinking about avoiding a conservative (expensive)
approach to design. Speeds are becoming such that those hopes are rarely
fulfilled anymore. Even reasonable engineering judgement isn't that great a
guide anymore and we are contemplating making whole-board simulations part of
our design process.
The common approach to design is to avoid the unpleasant (in this case no room
for termination networks or time for a new supplier) and end up with problems at
the back end of a design where cost factors are multiplied by 10 to 1000 (or
even more) to fix. Once again, I don't know if this was a factor.
What I have learned is this: Simulation as a board is being routed is too late
to find such problems. At that point they directly affect layout, schedules and
the viability of the project. At that point simulation should just be a
(virtual) verification check of previous good design choices. Per D.C. Sessions'
suggestion, simulation at the timing/topology choice stage with feedback to
supplier of a user modified/developed behavioral model to see if can be done,
is much timelier.
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