Re: [SI-LIST] : Terminating a bidirectional bus

Shayle Hirschman (shayle@mho.net)
Mon, 03 May 1999 12:12:16 -0500

May I add to your question what would the answer be if the FPGA and RAM are
3.3 v devices vs. 5 v devices? Would less of a voltage swing reduce the
need for termination, especially, as you are asking, on the data lines?

Shayle

At 09:21 AM 5/3/99 -0700, you wrote:
>Dear all,
>
>I would like to know you opinion on this issue. I am interfacing a
>state of the art FPGA with a high speed synchronous SRAM device. Since
>the interface is bidirectional (the FPGA will read and write data to
>the memory) I was wondering what is is the best way to terminate this
>bus. My intuition is that if the data lines are not very long, then a
>series termination near the FPGA end could have an effect similar to a
>series termination near the memory end when the memory is driving the
>bus.
>
>I've in the the standard SI book, and haven't found any hint on the
>problem.
>
>thanks in advance
>
>-Arrigo Benedetti
>--
>Dr. Arrigo Benedetti e-mail: arrigo@vision.caltech.edu
>Caltech, MS 136-93 phone: (626) 395-3695
>Pasadena, CA 91125 fax: (626) 795-8649
>
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