> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]]On Behalf Of Jin Zhao
> Sent: Thursday, September 23, 1999 2:09 PM
> To: [email protected], Eric Goodill; si-list
> Subject: Re: [SI-LIST] : Q: Plane-jumping return currents
>
>
> Hi Eric,
>
> The problem you raised on jumping reference planes can sometimes really
> become a serious signal integrity issue. Currents in vias between planes
> (such as those in stackup2) and passing through planes (such as those in
> stackup3) generate parallel plate-mode fields between planes. The
> parallel-plate mode fields propagate away from vias in the radial
> direction
> and can cause power and ground voltage fluctuations throughout the board.
> As been pointed out by Larry Smith in his yesterday's reply to your email,
> when a large number of nets switch simultaneously, significant damage to
> signal integrity can be caused by vias passing through planes. Actually,
> we've recently done a series of simulations, using SPEED97, on the effects
> of vias in the case of a large number of buses switching
> simultaneously, and
> on the effects of capacitors placed near vias. The report is at
> http://www.sigrity.com/infos/ApplicationExamples/app7.pdf. You can also
> download the report as well as reports of several other examples from our
> web site (www.sigrity.com). After entering our web site, click Support,
> then click "SPEED97 Application Examples".
>
> Regards,
>
> Jin Zhao
> Sigrity, Inc.
> 2105 Hamilton Ave. Suite 310
> San Jose, CA 95125
> Tel: 408-377-2180
> Fax: 408-377-2565
> ----- Original Message -----
> From: Eric Goodill <[email protected]>
> To: si-list <[email protected]>
> Sent: Tuesday, September 21, 1999 10:56 AM
> Subject: [SI-LIST] : Q: Plane-jumping return currents
>
>
> > Hi,
> >
> > Consider a few different partial stackups each with a via:
> >
> >
> > Stackup 1
> > | |----------- trace B
> > plane =========== | | ==========
> > trace A ------------| |
> >
> >
> > Stackup 2
> >
> > plane =========== | | ==========
> > trace A ------------| |
> > trace B | |-----------
> > plane =========== | | ==========
> >
> >
> > Stackup 3
> > | |----------- trace B
> > plane =========== | | ==========
> > plane =========== | | ==========
> > trace A ------------| |
> >
> >
> > In stackup 1, the return currents for trace A and trace B just need to
> > migrate to the other side of the the plane which is fairly easy
> and has a
> > low impedance. However, this stackup is not preferred for PCB
> > manufacturability reasons.
> >
> > In stackups 2 and 3, the return current for trace A moving to
> trace B has
> > to jump planes. The only place that can occur is via a
> capacitance. Some
> > capacitance is provided by the interplane capacitance which works better
> in
> > stackup 3 than it does in stackup 2. Otherwise, a nearby
> bypass cap must
> > be found. The farther away the cap is, the larger the inductance (and
> > impedance) of the return current path.
> >
> > My system is running pretty fast (> 1 Gbps).
> >
> > My questions:
> >
> > 1. Is what I've described generally true?
> >
> > 2. How could one analyze how far away a "nearby" cap can be and not
> degrade
> > the signal too much?
> >
> > 3. How does the value of the cap affect this? Clearly we want a low
> > inductance package. Do I just go for the largest capacitance
> that fits in
> > a low-inductance package?
> >
> > 4. How could one analyze if the interplane capacitance is sufficient for
> > this purpose?
> >
> > -Eric
> >
> > --
> >
> > Eric Goodill Cisco Systems M/S SJ-N2
> > mailto:[email protected] 170 W Tasman Dr
> > voice: (408) 527-3460 San Jose CA 95134-1706
> > fax: (408) 527-3460 (yes, the same)
> >
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