I agree that it is well established that any discrete components used to
bypass high frequency signals must be placed close to the load. It is a
simple matter of voltage drop across the series inductance when the load (
driver ) undergoes significant di/dt. I also agree that no matter what the
interconnect impedance, propagation delays will ultimately limit the
usefulness of capacitance in Kansas to a load in California.
However, with all of that said, I think that it is important to note how
adverse the inductive impedance of discrete devices is. Even the smaller
packages, 0402 / 0603 have inductances of typically 1nH. A single device
crosses 1 ohm at 160MHz, or 3nS risetime. Even if we use the reverse
aspect ratio caps, this improves by only about 1.5:1 to 2:1. If we packed
a typical BGA with bypass caps, we might get one 0603 for every eight to
ten drivers in a 400-500 pin package or even fewer for a 600+ pin package.
Assuming that 1/2 of the drivers switch simultaneously, we will experience
current steps well in excess of 100mA. For a pedestrian 3nS risetime, we
would suffer 100mV+ of disturbance. For real risetimes in the 0.5nS to 1nS
region life is much worse. Therefore, we have to rely on the plane
capacitance and fight the interconnect inductance to maintain stable power
supply voltage at our drivers.
To the extent that the Zycon approach provides significant capacitance
through drastically lower series inductance than we can get with discrete
parts, it is able to establish a much lower impedance floor AT HIGH
FREQUENCIES, sic edge rates. Mid, and low frequencies still require
adequate energy storage in the form of bulk capacitors.
Eric's algebra is straight out of second semester physics textbooks.
Capacitance is just e0 * EA/ED, as an observed phenomena. The energy
required to charge some capacitance is the integral of the charge times the
force ( voltage ) required to move that charge, which when evaluated yields
the square formula 1/2 CV^2.
Regards,
Steve
At 09:21 AM 6/15/99 +1000, you wrote:
>Seems to me that only the C 'close' to where it is required is of any
>use. C 'further away' means that the fast signals that can use it can't
>see it.
>
>Similar arguments were canvassed during the 'where to put the bypass
>cap' debate
>- 'the plane inductance is low' (lumped argument)
>- 'the time is short' (transmission line argument).
>
>The C carries the return signal current of one or both edges, and the
>spacing of C adds that much distance to the return route.
>
>At 100pf/in^2 then a few hundred pF are useful to the fastest
>components.
>
>There seems to be a problem with the Eric's algebra.
>For a fixed V:
>if C is proportional to 1/d
>and if E is proportional to C
>then
>E is proportional to 1/d.
>
>Jon.
>
>
>Steve,
>I agree except for your statement about capacitance being inversely
>proportional to the plane separation. In fact, the capacitance of a
>parallel plate capacitor is proportional to A/d (A=area of plates,
>d=separation). The energy storage, on the other hand is E=(1/2)*C*V^2,
>which is proportional to 1/d^2.
>Eric Sweetman
>
>> ----------
>> From: Steve Weir[SMTP:[email protected]]
>> Reply To: [email protected]
>> Sent: Friday, June 11, 1999 5:05 PM
>> To: [email protected]
>> Subject: Re: [SI-LIST] : How do you use buried capacitance?
>>
>> Chris,
>>
>> The theory is pretty straightforward, this is just a parallel plate
>> capacitor. The thrill is that Zycon offers a fairly thin dielectric,
>so
>> the capacitance is much better than what is possible with typical
>> fiberglass. For 10mil separation between planes, the approximate
>> capacitance is 100pF per square inch. With Zycon, the separation is
>> 2mils,
>> so we get 25X the capacitance per square inch = 2.5nF/"^2. Because
>this
>> is
>> a plate capacitor, it has very high bandwidth. Because it is
>distributed
>> across the PWB assembly, we get very good load sharing. This also
>helps
>> the return current coupling as the signal trace moves from one plane
>to
>> another.
>>
>> You will still need to use bulk capacitors for mid-frequency
>decoupling,
>> ie
>> some number of 100nF, and multi-microfarad caps.
>>
>> Regards
>> At 10:17 AM 6/11/99 -0700, you wrote:
>> >I understand the priciples behind buried capacitance. What I don't
>> >understand is how you use it when designing a board.
>> >
>> >Is it only used for decoupling?
>> >
>> >How do you figure out how much decoupling capacitance it is
>equivalent to
>> >for a particular IC?
>> >
>
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