Re: [SI-LIST] : RE: Another decoupling question

D. C. Sessions (dc.sessions@vlsi.com)
Mon, 20 Sep 1999 14:03:46 -0700

Sai Vishwanthaiah wrote:
>
> Hi,
>
> > Ah! I agree that providing I/O bypass capacitance on-chip is hideously
> > expensive, due in equal part to the huge amount of charge storage needed
> > and to the limited benefit it provides (essentially it allows the use of
> > both supply and ground wires to supply SSO transients instead of just one
> > or the other.)
> >
> > IMHO the best bet for minimizing SSO transients is to use balanced codes
> > such as 8b/10b so that there isn't any substantial common-mode current.
> > Actually saves pins and cuts jitter too.
>
> Can you please elaborate on what are "balanced codes such as 8b/10b" ?
> I've not heard about this before.

Assuming that you have to ship an 8-bit bus between two (or more) chips
at high speed. Better yet, assume that you have to ship 32 bits but are
running at the SSO-jitter limited rate and would prefer to narrow the bus
and run faster.

If you increase the number of data lines per byte from eight to ten and
encode the byte using an 8b/10b scheme (five high, five low almost all the
time) then there will be no net current in the terminator supply, and both
the positive and negative supply currents will remain constant. Without
net changes in supply current, there is no net di/dt and thus no ground
bounce, no induced noise on other busses, no slope modulation jitter, no
net mirror current, and a LOT less EMI.

Time was that this would have been timing-budget suicide because the coding
logic was a lot of real estate and time. Now that I/O dominates to a far
greater degree and core real estate is relative cheap, it makes a lot more
sense.

-- 
D. C. Sessions
dc.sessions@vlsi.com

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