Re: [SI-LIST] : Terminating a bidirectional bus

Poulet P. (poulet@fax.ussj.ricoh.com)
Mon, 03 May 1999 11:34:00 -0700

Arrigo,

For what it's worth. We fixed a very tough SI problem a few months ago using series termination on both ends (also not the same R value ) of a bi-directional board to board connection. The connection was a 8bit data bus extension.
Although the speed of the data transmission wasn't too high (2 Mbyte/s) we were able using this termination scheme to solve all the problems and increase the cable length (twisted pair 28awg) up to 15" long between the two boards.

One side has no transceiver at all, the other a simple AHCT244 and 245 IC's.
This method is nice and easy to implement but be careful with the increased delay due to RC response of the termination.
I must say that the SI list helped us a lot in understanding and solving the problem.
Thanks to all

Arrigo Benedetti wrote:

> Dear all,
>
> I would like to know you opinion on this issue. I am interfacing a
> state of the art FPGA with a high speed synchronous SRAM device. Since
> the interface is bidirectional (the FPGA will read and write data to
> the memory) I was wondering what is is the best way to terminate this
> bus. My intuition is that if the data lines are not very long, then a
> series termination near the FPGA end could have an effect similar to a
> series termination near the memory end when the memory is driving the
> bus.
>
> I've in the the standard SI book, and haven't found any hint on the
> problem.
>
> thanks in advance
>
> -Arrigo Benedetti
> --
> Dr. Arrigo Benedetti e-mail: arrigo@vision.caltech.edu
> Caltech, MS 136-93 phone: (626) 395-3695
> Pasadena, CA 91125 fax: (626) 795-8649
>
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--
Philippe Poulet
Hardware Engineer
RICOH Corp
3001 Orchard Pkwy
San Jose CA95134-2088
Ph: (408) 944-3347
Fax: (408) 434-5390

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