Similar arguments were canvassed during the 'where to put the bypass
- 'the plane inductance is low' (lumped argument)
- 'the time is short' (transmission line argument).
The C carries the return signal current of one or both edges, and the
spacing of C adds that much distance to the return route.
At 100pf/in^2 then a few hundred pF are useful to the fastest
There seems to be a problem with the Eric's algebra.
For a fixed V:
if C is proportional to 1/d
and if E is proportional to C
E is proportional to 1/d.
I agree except for your statement about capacitance being inversely
proportional to the plane separation. In fact, the capacitance of a
parallel plate capacitor is proportional to A/d (A=area of plates,
d=separation). The energy storage, on the other hand is E=(1/2)*C*V^2,
which is proportional to 1/d^2.
> From: Steve Weir[SMTP:email@example.com]
> Reply To: firstname.lastname@example.org
> Sent: Friday, June 11, 1999 5:05 PM
> To: email@example.com
> Subject: Re: [SI-LIST] : How do you use buried capacitance?
> The theory is pretty straightforward, this is just a parallel plate
> capacitor. The thrill is that Zycon offers a fairly thin dielectric,
> the capacitance is much better than what is possible with typical
> fiberglass. For 10mil separation between planes, the approximate
> capacitance is 100pF per square inch. With Zycon, the separation is
> so we get 25X the capacitance per square inch = 2.5nF/"^2. Because
> a plate capacitor, it has very high bandwidth. Because it is
> across the PWB assembly, we get very good load sharing. This also
> the return current coupling as the signal trace moves from one plane
> You will still need to use bulk capacitors for mid-frequency
> some number of 100nF, and multi-microfarad caps.
> At 10:17 AM 6/11/99 -0700, you wrote:
> >I understand the priciples behind buried capacitance. What I don't
> >understand is how you use it when designing a board.
> >Is it only used for decoupling?
> >How do you figure out how much decoupling capacitance it is
> >for a particular IC?
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