I'd like to know if any of you had better luck in doing signal
integrity simulations with ZBT SRAMs. I am simulating a
bidirectional data bus between a ZBT and a Xilinx Virtex device. What
is strange is that the rise time of the ZBT driver is slow
compared to the clock period even for model files of devices in the
166-200 MHz clock frequency range. I tried IBIS files from Micron, IDT
and Cypress and the 10-90% rise time is always in the 1.1-2.4 ns. One
of these models is so slow that at 166 MHz the voltage on the line
does not even reach VDD.
Any ideas ?
Thanks in advance
-- Dr. Arrigo Benedetti o e-mail: email@example.com Caltech, MS 136-93 < > phone: (626) 395-3695 Pasadena, CA 91125 / \ fax: (626) 795-8649-- We choose to go to the moon in this decade and do the other things not because they are easy, but because they are hard. - John F. Kennedy
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