RE: [SI-LIST] : response to semiconductor I/O edge rates

Haller, Robert (Robert.Haller@compaq.com)
Fri, 16 Jul 1999 15:59:17 -0400

Roy,
Ok, It's my turn to 'beat a dead horse' Having fought this issue
before, I can't resist but add my own opinion.

If your edge rate is less then 5% of your cycle time the fast edge creates
more problems than benefits. I have been lucky and work side by side with
ASIC I/O cell designers. We look at early versions of cells (spice models)
and determine compatibility with the board environment. We sometimes make
recommendations and fight for new cell versions when applicable. With
reduced cycle times and tighter product schedules, higher ASIC pinout,
higher di/dt's and in general noisier board environments, it is imperative
to optimize I/O cell edge rates. When selecting jelly beans this is a
critical area. I would also recommend spending time in the lab breadboarding
and/or building test chips to prevent painful months in the lab with a scope
probe in your hands.

Depending on what you are designing, you eventually will reach the point
where whole board simulations are necessary. We have been doing it for some
time and it helps prevent many issues/problems that can creep into a design.
But whole board analysis is no substitute for good up front SI what if
analysis.

I also agree with D.C. and think we should blow up the ancient carving of
the 50 pf standard load on that cave wall. :-)

just my $0.02
bob

Robert J. Haller
Compaq Computer Corporation
AlphaServer Product Development
Phone: (978) 493-4112
Fax: (978) 493-0941
robert.haller@compaq.com

-----Original Message-----
From: Roy Leventhal [mailto:Roy_Leventhal@mw.3com.com]
Sent: Friday, July 16, 1999 9:36 AM
To: si-list@silab.eng.sun.com
Subject: RE: [SI-LIST] : response to semiconductor I/O edge rates

Tom,

The simple answer is that this is a big, proprietary development ASIC. The
designer never had any intention that it should have such a fast edge rate.
As
a matter of prudent checking he had me check the signal integrity once we
got
the IBIS model and partially routed board. That's when we discovered that
the
edge rate was so fast. The semiconductor house had never given us a heads-up
that the edge rate was likely to be so fast. Or so I understand it. Now the
semi
house is telling us they can't do anything about it.

It is possible that the circuit designer knew about the edge rate earlier
than I
think and was hoping that some simulation or layout/routing magic pixy dust
would be sprinkled on his circuit. I don't think I'll ever know the answer
to
that. I do see wishful thinking about avoiding a conservative (expensive)
approach to design. Speeds are becoming such that those hopes are rarely
fulfilled anymore. Even reasonable engineering judgement isn't that great a
guide anymore and we are contemplating making whole-board simulations part
of
our design process.

The common approach to design is to avoid the unpleasant (in this case no
room
for termination networks or time for a new supplier) and end up with
problems at
the back end of a design where cost factors are multiplied by 10 to 1000 (or
even more) to fix. Once again, I don't know if this was a factor.

What I have learned is this: Simulation as a board is being routed is too
late
to find such problems. At that point they directly affect layout, schedules
and
the viability of the project. At that point simulation should just be a
(virtual) verification check of previous good design choices. Per D.C.
Sessions'
suggestion, simulation at the timing/topology choice stage with feedback to
supplier of a user modified/developed behavioral model to see if can be
done,
is much timelier.

Best Regards,

Roy

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